cpu/intel/common: decouple IA32_FEATURE_CONTROL lock from set_vmx()

Newer CPUs/SoCs need to configure other features via the
IA32_FEATURE_CONTROL msr, such as SGX, which cannot be done if the
msr is already locked. Create separate functions for setting the
vmx flag and lock bit, and rename existing function to indicate that
the lock bit will be set in addition to vmx flag (per Kconfig).

This will allow Skylake/Kabylake (and others?) to use the common
VMX code without breaking SGX, while ensuring no change in functionality
to existing platforms which current set both together.

Test: build/boot each affected platform, ensure no change in functionality

Change-Id: Iee772fe87306b4729ca012cef8640d3858e2cb06
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30229
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 35 insertions, 11 deletions

diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig
index 739333e4aa0c..56bed22a1aa1 100644
--- a/src/cpu/intel/common/Kconfig
+++ b/src/cpu/intel/common/Kconfig
@@ -7,9 +7,8 @@ config ENABLE_VMX
 	bool "Enable VMX for virtualization"
 	default y
 
-config SET_VMX_LOCK_BIT
-	bool "Set lock bit after configuring VMX"
-	depends on ENABLE_VMX
+config SET_IA32_FC_LOCK_BIT
+	bool "Set IA32_FEATURE_CONTROL lock bit"
 	default y
 	help
 	  Although the Intel manual says you must set the lock bit in addition
diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h
index 81c9f16d1981..b9ac0566c62b 100644
--- a/src/cpu/intel/common/common.h
+++ b/src/cpu/intel/common/common.h
@@ -15,7 +15,9 @@
 #ifndef _CPU_INTEL_COMMON_H
 #define _CPU_INTEL_COMMON_H
 
-void set_vmx(void);
+void set_vmx_and_lock(void);
+void set_feature_ctrl_vmx(void);
+void set_feature_ctrl_lock(void);
 
 /*
  * Init CPPC block with MSRs for Intel Enhanced Speed Step Technology.
diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
index 7dbbfda2e8fe..9c0fcbb12297 100644
--- a/src/cpu/intel/common/common_init.c
+++ b/src/cpu/intel/common/common_init.c
@@ -21,12 +21,17 @@
 #include <cpu/x86/msr.h>
 #include "common.h"
 
-void set_vmx(void)
+void set_vmx_and_lock(void)
+{
+	set_feature_ctrl_vmx();
+	set_feature_ctrl_lock();
+}
+
+void set_feature_ctrl_vmx(void)
 {
 	msr_t msr;
 	uint32_t feature_flag;
 	int enable = IS_ENABLED(CONFIG_ENABLE_VMX);
-	int lock = IS_ENABLED(CONFIG_SET_VMX_LOCK_BIT);
 
 	feature_flag = cpu_get_feature_flags_ecx();
 	/* Check that the VMX is supported before reading or writing the MSR. */
@@ -38,10 +43,10 @@ void set_vmx(void)
 	msr = rdmsr(IA32_FEATURE_CONTROL);
 
 	if (msr.lo & (1 << 0)) {
-		printk(BIOS_ERR, "VMX is locked, so %s will do nothing\n",
+		printk(BIOS_ERR, "IA32_FEATURE_CONTROL is locked, so %s will do nothing\n",
 			__func__);
-		/* VMX locked. If we set it again we get an illegal
-		 * instruction
+		/* IA32_FEATURE_CONTROL locked. If we set it again we get an
+		 * illegal instruction
 		 */
 		return;
 	}
@@ -59,14 +64,32 @@ void set_vmx(void)
 
 	wrmsr(IA32_FEATURE_CONTROL, msr);
 
+	printk(BIOS_DEBUG, "VMX status: %s\n",
+		enable ? "enabled" : "disabled");
+}
+void set_feature_ctrl_lock(void)
+{
+	msr_t msr;
+	int lock = IS_ENABLED(CONFIG_SET_IA32_FC_LOCK_BIT);
+
+	msr = rdmsr(IA32_FEATURE_CONTROL);
+
+	if (msr.lo & (1 << 0)) {
+		printk(BIOS_ERR, "IA32_FEATURE_CONTROL is locked, so %s will do nothing\n",
+			__func__);
+		/* IA32_FEATURE_CONTROL locked. If we set it again we get an
+		 * illegal instruction
+		 */
+		return;
+	}
+
 	if (lock) {
 		/* Set lock bit */
 		msr.lo |= (1 << 0);
 		wrmsr(IA32_FEATURE_CONTROL, msr);
 	}
 
-	printk(BIOS_DEBUG, "VMX status: %s, %s\n",
-		enable ? "enabled" : "disabled",
+	printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL status: %s\n",
 		lock ? "locked" : "unlocked");
 }