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| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-03-28 11:32:58 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-30 18:49:15 +0000 |
| commit | 2276d4f4a858da4a1cccc7cd8d870f0ac114efed (patch) | |
| tree | bc96f520ceb72e6aba761a3515da58a0f9c752a8 /src/cpu/intel/microcode | |
| parent | 4f9ff53e4239426d06c5a55a9e04b0e9a3e801cc (diff) | |
| download | coreboot-2276d4f4a858da4a1cccc7cd8d870f0ac114efed.tar.gz coreboot-2276d4f4a858da4a1cccc7cd8d870f0ac114efed.tar.bz2 coreboot-2276d4f4a858da4a1cccc7cd8d870f0ac114efed.zip | |
soc/intel/common: Add support to configure top swap feature
RTC BUC control register provides a software interface to
configure the top swap feature. This patch adds implementation
to enable/disable top swap feature and gets it accessible in
romstage as well.
The top swap control functions are exposed only if INTEL_HAS_TOP_SWAP
is selected.
To use the topswap feature a second bootblock has to be added
to the cbfs. Below configs aid in doing that,
INTEL_HAS_TOP_SWAP
INTEL_ADD_TOP_SWAP_BOOTBLOCK
INTEL_TOP_SWAP_BOOTBLOCK_SIZE
Enabling and Disabling topswap, using the added API enables user
to boot alternatively from either bootblock.
Change-Id: Iea31b891f81e76d4d623fcb68183c3ad3dcadbad
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/25805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/microcode')
0 files changed, 0 insertions, 0 deletions