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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-25 21:37:40 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-31 10:35:42 +0000 |
| commit | af1cbe2278b4ca3252d48ba36814db940e9d4237 (patch) | |
| tree | a342792a4d174736967049441822729c2e2954be /src/cpu/intel/model_206ax/finalize.c | |
| parent | 9a100b5c1df00b4b4570f914412068e3d86343f4 (diff) | |
| download | coreboot-af1cbe2278b4ca3252d48ba36814db940e9d4237.tar.gz coreboot-af1cbe2278b4ca3252d48ba36814db940e9d4237.tar.bz2 coreboot-af1cbe2278b4ca3252d48ba36814db940e9d4237.zip | |
cpu/x86: make set_msr_bit publicly available
Haswell and model_2065 implement a static set_msr_bit helper which
should be publicly available instead. Move it to cpu/x86.
Change-Id: I68b314c917f15fc6e5351de1c539d5a3ae646df8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36338
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_206ax/finalize.c')
| -rw-r--r-- | src/cpu/intel/model_206ax/finalize.c | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index c9d53769b3de..d51fb2184755 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -23,23 +23,6 @@ * Document Number 504790 * Revision 1.6.0, June 2012 */ -static void msr_set_bit(unsigned int reg, unsigned int bit) -{ - msr_t msr = rdmsr(reg); - - if (bit < 32) { - if (msr.lo & (1 << bit)) - return; - msr.lo |= 1 << bit; - } else { - if (msr.hi & (1 << (bit - 32))) - return; - msr.hi |= 1 << (bit - 32); - } - - wrmsr(reg, msr); -} - void intel_model_206ax_finalize_smm(void) { /* Lock C-State MSR */ |