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| author | Sameer Nanda <snanda@chromium.org> | 2012-07-25 16:11:40 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-07 03:57:19 +0100 |
| commit | d16d576524d3b9346b72b30c5b50cec4712e4cb0 (patch) | |
| tree | 56e725ae09a431c5567f00f20adf3a5e9695ad8c /src/cpu/intel/model_206ax/finalize.c | |
| parent | b578627f5101d57103a66ade89863821254af89e (diff) | |
| download | coreboot-d16d576524d3b9346b72b30c5b50cec4712e4cb0.tar.gz coreboot-d16d576524d3b9346b72b30c5b50cec4712e4cb0.tar.bz2 coreboot-d16d576524d3b9346b72b30c5b50cec4712e4cb0.zip | |
Leave power control registers unlocked
To allow easy experimentation with thermals, leave power control
registers unlocked.
Change-Id: Ia53065f3f220c2faed58e7d53e60c3f169ae58ec
Signed-off-by: Sameer Nanda <snanda@chromium.org>
Reviewed-on: http://review.coreboot.org/1688
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/cpu/intel/model_206ax/finalize.c')
| -rw-r--r-- | src/cpu/intel/model_206ax/finalize.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 68cef8d782ae..4ed5d1e5f884 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -49,11 +49,24 @@ void intel_model_206ax_finalize_smm(void) if (cpuid_ecx(1) & (1 << 25)) msr_set_bit(MSR_FEATURE_CONFIG, 0); +#ifdef LOCK_POWER_CONTROL_REGISTERS + /* + * Lock the power control registers. + * + * These registers can be left unlocked if modifying power + * limits from the OS is desirable. Modifying power limits + * from the OS can be especially useful for experimentation + * during early phases of system bringup while the thermal + * power envelope is being proven. + */ + msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31); msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31); msr_set_bit(MSR_PKG_POWER_LIMIT, 63); msr_set_bit(MSR_PP0_POWER_LIMIT, 31); msr_set_bit(MSR_PP1_POWER_LIMIT, 31); +#endif + msr_set_bit(MSR_MISC_PWR_MGMT, 22); msr_set_bit(MSR_LT_LOCK_MEMORY, 0); } |