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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-02 08:44:47 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-05 01:38:15 +0000 |
| commit | 4e6b7907de07c9c7d4b01a6213a8e13e946398cb (patch) | |
| tree | d6cb8f208a588506710e36a38d141d9228af7483 /src/cpu/intel/model_6fx | |
| parent | 19c0ae540ea992b76eb65421381269def0a6328d (diff) | |
| download | coreboot-4e6b7907de07c9c7d4b01a6213a8e13e946398cb.tar.gz coreboot-4e6b7907de07c9c7d4b01a6213a8e13e946398cb.tar.bz2 coreboot-4e6b7907de07c9c7d4b01a6213a8e13e946398cb.zip | |
src: Fix MSR_PKG_CST_CONFIG_CONTROL register name
Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/cpu/intel/model_6fx')
| -rw-r--r-- | src/cpu/intel/model_6fx/model_6fx_init.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index a1433f6de10f..642201cc5e5b 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -33,7 +33,7 @@ static void configure_c_states(void) { msr_t msr; - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // config lock until next reset msr.lo |= (1 << 14); // Deeper Sleep msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States @@ -44,7 +44,7 @@ static void configure_c_states(void) msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; |