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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2012-06-27 16:14:49 +0300 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2012-07-02 15:49:07 +0200 |
| commit | 9ed1456eff73d1a268eabb84176dd2a2107bf2d7 (patch) | |
| tree | 9811746255b0c2b168f15b76e1375d91280beb28 /src/cpu/intel/model_f4x/model_f4x_init.c | |
| parent | ac6e3172ff7c1c11da59c488b239d08af1248503 (diff) | |
| download | coreboot-9ed1456eff73d1a268eabb84176dd2a2107bf2d7.tar.gz coreboot-9ed1456eff73d1a268eabb84176dd2a2107bf2d7.tar.bz2 coreboot-9ed1456eff73d1a268eabb84176dd2a2107bf2d7.zip | |
Intel CPUs: execute microcode update only once per core
Early HT-enabled CPUs do not serialize microcode updates within a core.
Solve this by running microcode updates on the thread with the smallest
lapic ID of a core only.
Also set MTRRs once per core only.
Change-Id: I6a3cc9ecec2d8e0caed29605a9b19ec35a817620
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1142
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_f4x/model_f4x_init.c')
| -rw-r--r-- | src/cpu/intel/model_f4x/model_f4x_init.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index 54edf2e335ac..f3f0b2af0f6f 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -39,11 +39,15 @@ static void model_f4x_init(device_t cpu) { /* Turn on caching if we haven't already */ x86_enable_cache(); - x86_setup_mtrrs(); - x86_mtrr_check(); - /* Update the microcode */ - intel_update_microcode(microcode_updates); + if (!intel_ht_sibling()) { + /* MTRRs are shared between threads */ + x86_setup_mtrrs(); + x86_mtrr_check(); + + /* Update the microcode */ + intel_update_microcode(microcode_updates); + } /* Enable the local cpu apics */ setup_lapic(); |