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authorKyösti Mälkki <kyosti.malkki@gmail.com>2023-06-30 18:44:26 +0300
committerFelix Held <felix-coreboot@felixheld.de>2023-07-06 13:54:20 +0000
commita52b93b262582009decf924dbdde9bc1bf856ddb (patch)
treec1bb9a7ef4c8abe5d82381f6c160741a620ab33a /src/cpu/x86/Kconfig
parent053a45bcdb3ccf8a686b35c97e8404c386f65d58 (diff)
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cpu/x86: Add some notes about XAPIC/X2APIC
At the time of writing SMM runtime does not make register accesses to LAPIC registers, but such breakage has been reported. S3 resume failure, where OS switched back from X2APIC to XAPIC mode, can be reproduced with a sandybridge SKU that has VT-d disabled. Change-Id: I300ba87c3d8fde548dbaf95703bd7e2fe54cff57 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/cpu/x86/Kconfig')
-rw-r--r--src/cpu/x86/Kconfig10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 1e1b2ac1579a..4e17690cc31a 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -50,16 +50,26 @@ choice
config XAPIC_ONLY
prompt "Set XAPIC mode"
bool
+ help
+ coreboot and SMM runtime only use XAPIC mode.
+ FIXME: DMAR should have X2APIC optout bit set.
config X2APIC_ONLY
prompt "Set X2APIC mode"
bool
depends on PARALLEL_MP
+ help
+ coreboot and SMM runtime only use X2APIC mode.
+ Note: OS switches back to XAPIC mode if VT-d is disabled.
+ FIXME: S3 resume (and SMM runtime) will break if OS makes the switch.
config X2APIC_RUNTIME
prompt "Support both XAPIC and X2APIC"
bool
depends on PARALLEL_MP
+ help
+ The switch to X2APIC mode happens early in ramstage. SMM runtime can
+ support either mode in case the OS switches back to XAPIC.
config X2APIC_LATE_WORKAROUND
prompt "Use XAPIC for AP bringup, then change to X2APIC"