diff options
| author | Ashish Kumar Mishra <ashish.k.mishra@intel.com> | 2024-01-16 16:23:03 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-08 13:02:34 +0000 |
| commit | ecbc243a45de3b7894e2fe6c8e22b5d07172274b (patch) | |
| tree | 6fffd581ee5293c58d5a48723ecc7b08c564bc6a /src/cpu/x86/Kconfig | |
| parent | 32ebaef73c8e1cc367e1c63af587250041fce32a (diff) | |
| download | coreboot-ecbc243a45de3b7894e2fe6c8e22b5d07172274b.tar.gz coreboot-ecbc243a45de3b7894e2fe6c8e22b5d07172274b.tar.bz2 coreboot-ecbc243a45de3b7894e2fe6c8e22b5d07172274b.zip | |
cpu/x86: Add 1GiB pages for memory access up to 512GiB
Current pagetable implementation allows memory access up to 4GiB using
2MiB pages. If user wants to access more than 4GiB with a 2MiB page it
will require more pagetable entries. By using a 1GiB page table, users
can access more than 4GiB of memory while reducing the number of
pagetable entries. This patch enables memory access up to 512GiB through
1GiB pages by selecting USE_1G_PAGES_TLB in Kconfig.
TEST: Verified in 64bit mode boot and access above 4GiB
Change-Id: Id569ae5b50abf5b72e4db33b5e4cd802399e76ec
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80088
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu/x86/Kconfig')
| -rw-r--r-- | src/cpu/x86/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 4e17690cc31a..6c784b4c5dad 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -150,6 +150,13 @@ config NO_SMM bool default n +config USE_1G_PAGES_TLB + bool + default n + help + Select this option to enable access to up to 512 GiB of memory + by using 1 GiB large pages. + config SMM_ASEG bool default n |