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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-05-14 01:22:30 +0200 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-10-28 21:28:18 +0000 |
| commit | 48c825ebd1beadb8ac4fd3ae687a36ff4705ab7a (patch) | |
| tree | 6dbd2890317fa87a12121f7f17c671d40c6ab190 /src/cpu/x86/mp_init.c | |
| parent | 49d014f7a043392640f5247912c344982c42ca46 (diff) | |
| download | coreboot-48c825ebd1beadb8ac4fd3ae687a36ff4705ab7a.tar.gz coreboot-48c825ebd1beadb8ac4fd3ae687a36ff4705ab7a.tar.bz2 coreboot-48c825ebd1beadb8ac4fd3ae687a36ff4705ab7a.zip | |
cpu/x86/mp_init.c: Use linked list data structures
There is no need to keep track of device structures separately.
Change-Id: Ie728110fc8c60fec94ae4bedf74e17740cf78f67
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/cpu/x86/mp_init.c')
| -rw-r--r-- | src/cpu/x86/mp_init.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index dd9dedabd086..e3b294fc7953 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -107,7 +107,7 @@ struct saved_msr { /* The sipi vector rmodule is included in the ramstage using 'objdump -B'. */ extern char _binary_sipi_vector_start[]; -/* The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is at the +/* The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is that the * memory range is already reserved so the OS cannot use it. That region is * free to use for AP bringup before SMM is initialized. */ static const uintptr_t sipi_vector_location = SMM_DEFAULT_BASE; @@ -121,9 +121,6 @@ struct mp_flight_plan { static int global_num_aps; static struct mp_flight_plan mp_info; -/* Keep track of device structure for each CPU. */ -static struct device *cpus_dev[CONFIG_MAX_CPUS]; - static inline void barrier_wait(atomic_t *b) { while (atomic_read(b) == 0) @@ -175,6 +172,8 @@ static void park_this_cpu(void *unused) stop_this_cpu(); } +static struct bus *g_cpu_bus; + /* By the time APs call ap_init() caching has been setup, and microcode has * been loaded. */ static void asmlinkage ap_init(void) @@ -185,7 +184,11 @@ static void asmlinkage ap_init(void) enable_lapic(); setup_lapic_interrupts(); - info->cpu = cpus_dev[info->index]; + struct device *dev = g_cpu_bus->children; + for (unsigned int i = info->index; i > 0; i--) + dev = dev->sibling; + + info->cpu = dev; cpu_add_map_entry(info->index); @@ -384,7 +387,6 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p) continue; } new->name = processor_name; - cpus_dev[i] = new; } return max_cpus; @@ -579,6 +581,8 @@ static enum cb_err mp_init(struct bus *cpu_bus, struct mp_params *p) int num_cpus; atomic_t *ap_count; + g_cpu_bus = cpu_bus; + init_bsp(cpu_bus); if (p == NULL || p->flight_plan == NULL || p->num_records < 1) { |