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| author | Duncan Laurie <dlaurie@chromium.org> | 2012-07-16 12:11:53 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-26 20:31:52 +0200 |
| commit | 0eefa005030a70f5c691155b931bb778ad1fb2ae (patch) | |
| tree | a35355b720a90d13223939b3abc5f6a7658075f0 /src/cpu | |
| parent | 10d31aba76a0a0fd3fd79d32698c2634a4293add (diff) | |
| download | coreboot-0eefa005030a70f5c691155b931bb778ad1fb2ae.tar.gz coreboot-0eefa005030a70f5c691155b931bb778ad1fb2ae.tar.bz2 coreboot-0eefa005030a70f5c691155b931bb778ad1fb2ae.zip | |
ACPI: Add function to write _PPC using NVS
The existing NVS variable for PPCM will be used to
select a dynamic max P-state.
By itself this does not change existing behavior because
the NVS PPCM variable is initialized to zero.
PPCM can be tested by building and booting a modified BIOS
that sets gnvs->ppcm to a value greater than 1 and checking
from the OS that the P-state is limited to that value.
Change-Id: Ia7b3bbc6b84c1aa42349bb236abee5cc92486561
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1341
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/model_206ax/acpi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 9784c4771f90..f66df51a2aa2 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -251,7 +251,7 @@ static int generate_P_state_entries(int core, int cores_per_package) len = acpigen_write_empty_PCT(); /* Write _PPC with no limit on supported P-state */ - len += acpigen_write_PPC(0); + len += acpigen_write_PPC_NVS(); /* Write PSD indicating configured coordination type */ len += acpigen_write_PSD_package(core, cores_per_package, coord_type); |