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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-01 10:12:45 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-19 09:28:55 +0000 |
| commit | 5a157176dd8787aed39a8d14691ba536bee08dcf (patch) | |
| tree | f67cd11dcf0d1855cf38438b06ac7440f05d1a0b /src/cpu | |
| parent | 7841a7f82416e6ad1d00610cca43a3fa9cc6b320 (diff) | |
| download | coreboot-5a157176dd8787aed39a8d14691ba536bee08dcf.tar.gz coreboot-5a157176dd8787aed39a8d14691ba536bee08dcf.tar.bz2 coreboot-5a157176dd8787aed39a8d14691ba536bee08dcf.zip | |
cpu/x86/lapic: Refactor timer_fsb()
Common apic_timer code in cpu/x86 should not depend on
intel header files.
Change-Id: Ib099921d4b8e561daea47219385762bb00fc4548
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34091
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/common/fsb.c | 29 | ||||
| -rw-r--r-- | src/cpu/x86/lapic/apic_timer.c | 39 |
2 files changed, 24 insertions, 44 deletions
diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index d66e87a396f9..2d86abd92962 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -11,12 +11,16 @@ * GNU General Public License for more details. */ +#include <arch/early_variables.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/fsb.h> #include <console/console.h> #include <commonlib/helpers.h> +#include <delay.h> + +static u32 g_timer_fsb CAR_GLOBAL; static int get_fsb(void) { @@ -67,16 +71,31 @@ static int get_fsb(void) return ret; } -int get_ia32_fsb(void) +static int set_timer_fsb(void) { - int ret; + int ret = get_fsb(); - ret = get_fsb(); + if (ret > 0) { + car_set_var(g_timer_fsb, ret); + return 0; + } if (ret == -1) printk(BIOS_ERR, "FSB not found\n"); if (ret == -2) printk(BIOS_ERR, "CPU not supported\n"); - return ret; + return -1; +} + +u32 get_timer_fsb(void) +{ + u32 fsb; + + fsb = car_get_var(g_timer_fsb); + if (fsb > 0) + return fsb; + + set_timer_fsb(); + return car_get_var(g_timer_fsb); } /** @@ -87,7 +106,7 @@ int get_ia32_fsb(void) */ int get_ia32_fsb_x3(void) { - const int fsb = get_ia32_fsb(); + const int fsb = get_timer_fsb(); if (fsb > 0) return 100 * DIV_ROUND_CLOSEST(3 * fsb, 100); diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 83521b723071..58836b5e3fa5 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -17,44 +17,8 @@ #include <thread.h> #include <arch/cpu.h> #include <arch/early_variables.h> -#include <cpu/intel/fsb.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> -#include <cpu/intel/speedstep.h> - -/* NOTE: This code uses global variables, so it can not be used during - * memory init. - */ - -#if CONFIG_UDELAY_LAPIC_FIXED_FSB != 0 -static inline u32 get_timer_fsb(void) -{ - return CONFIG_UDELAY_LAPIC_FIXED_FSB; -} - -static int set_timer_fsb(void) -{ - return 0; -} -#else -static u32 g_timer_fsb CAR_GLOBAL; - -static int set_timer_fsb(void) -{ - int ia32_fsb = get_ia32_fsb(); - - if (ia32_fsb > 0) { - car_set_var(g_timer_fsb, ia32_fsb); - return 0; - } - return -1; -} - -static inline u32 get_timer_fsb(void) -{ - return car_get_var(g_timer_fsb); -} -#endif void init_timer(void) { @@ -66,9 +30,6 @@ void init_timer(void) /* Set the initial counter to 0xffffffff */ lapic_write(LAPIC_TMICT, 0xffffffff); - - /* Set FSB frequency to a reasonable value */ - set_timer_fsb(); } void udelay(u32 usecs) |