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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-06-13 20:34:54 +0300 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-06-15 19:14:13 +0000 |
| commit | 61ba7fb2d9ecd2cfd64dda0618d544e4429fee8e (patch) | |
| tree | de32fc507063e0aa1e4a8fbdc4519f5e733f652c /src/cpu | |
| parent | 44ef38f70344f44ee53a3883515246172eb75054 (diff) | |
| download | coreboot-61ba7fb2d9ecd2cfd64dda0618d544e4429fee8e.tar.gz coreboot-61ba7fb2d9ecd2cfd64dda0618d544e4429fee8e.tar.bz2 coreboot-61ba7fb2d9ecd2cfd64dda0618d544e4429fee8e.zip | |
cpu/intel: Remove obsolete comment in CAR setup
A looong time ago when cache_as_ram.S was built into romstage,
the stage was also linked twice. First at a fixed low address
and then again relocated at the final execute-in-place address.
Change-Id: Ic624feef6794f2c24e38459a45583d84fc07a484
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/car/core2/cache_as_ram.S | 4 | ||||
| -rw-r--r-- | src/cpu/intel/car/p3/cache_as_ram.S | 4 | ||||
| -rw-r--r-- | src/cpu/intel/car/p4-netburst/cache_as_ram.S | 4 |
3 files changed, 0 insertions, 12 deletions
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 3183cc6e0635..837394c8c9a3 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -132,10 +132,6 @@ addrsize_set_high: /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html - */ movl $_program, %eax andl $_xip_mtrr_mask, %eax orl $MTRR_TYPE_WRPROT, %eax diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 259e321c3850..71e344778f75 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -121,10 +121,6 @@ addrsize_set_high: /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html - */ movl $_program, %eax andl $_xip_mtrr_mask, %eax orl $MTRR_TYPE_WRPROT, %eax diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 806102f0b002..4e365384141f 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -322,10 +322,6 @@ cache_rom: /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html - */ movl $_program, %eax andl $_xip_mtrr_mask, %eax orl $MTRR_TYPE_WRPROT, %eax |