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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-02-10 07:13:29 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-02-11 13:53:56 +0000 |
| commit | 707e5452e7037bfc918862901401608469d2e86a (patch) | |
| tree | 55546b314230e3769ebdb02ac59a81a6b418bacf /src/cpu | |
| parent | ed04aab8134531d5baad75fc8e35f73147863440 (diff) | |
| download | coreboot-707e5452e7037bfc918862901401608469d2e86a.tar.gz coreboot-707e5452e7037bfc918862901401608469d2e86a.tar.bz2 coreboot-707e5452e7037bfc918862901401608469d2e86a.zip | |
cpu/x86/lapic: Fix SMP=n case with LEGACY_SMP_INIT
Fix regression after commit 9ec7227c9b
cpu/x86/lapic: Move LAPIC configuration to MP init
The call to disable_lapic() got removed and with asus/p2b
SeaBIOS payload was unable to load kernel.
The combination of entering SeaBIOS payload with an
enabled lapic but not having programmed LAPIC_LVT0
for DELIVERY_MODE_EXTINT apparently disconnects i8259
PIC interrupt delivery pin.
Change-Id: If51e5d65153a02ac7af191e7897c04bd4e298006
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/x86/lapic/lapic_cpu_init.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 837d32f3b6a3..2cb84594e9f1 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -384,6 +384,8 @@ void initialize_cpus(struct bus *cpu_bus) if (is_smp_boot()) { enable_lapic(); setup_lapic_interrupts(); + } else { + disable_lapic(); } /* Get the device path of the boot CPU */ |