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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-04-07 15:10:35 +0200 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-04-11 08:48:34 +0000 |
| commit | bc749a068ad8640497abb1985f0ccfdd66cd5ffb (patch) | |
| tree | 37b10c4e7ccb94f534f4d7cd6ea368db8841a042 /src/cpu | |
| parent | dccfb8a2158287be48522f9f70fd3e83b84c671f (diff) | |
| download | coreboot-bc749a068ad8640497abb1985f0ccfdd66cd5ffb.tar.gz coreboot-bc749a068ad8640497abb1985f0ccfdd66cd5ffb.tar.bz2 coreboot-bc749a068ad8640497abb1985f0ccfdd66cd5ffb.zip | |
soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding
Some Super I/Os may be strapped to respond on the secondary ports
0x4e/0x4f. Enable them early so that mainboard is able to initialize
a serial port for example.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6df158f54a48fb9f3173a4b209316c8116aa265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/cpu')
0 files changed, 0 insertions, 0 deletions