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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2020-09-28 22:31:06 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-07 05:49:10 +0000 |
| commit | c439e07936b95a613bc949d84c562dc5e7680760 (patch) | |
| tree | 87952b6b2e09654a1eb5b31eaa11e87160c206d0 /src/cpu | |
| parent | 6edaa216982196a675a798d85e59418565cc3c92 (diff) | |
| download | coreboot-c439e07936b95a613bc949d84c562dc5e7680760.tar.gz coreboot-c439e07936b95a613bc949d84c562dc5e7680760.tar.bz2 coreboot-c439e07936b95a613bc949d84c562dc5e7680760.zip | |
cpu/intel/car/core2/cache_as_ram: Add x86_64 support
Tested on Lenovo T500 with additional patches.
Change-Id: I27cdec5f112588b219f51112279b2dfbb05b6c97
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram_symbols.inc | 3 | ||||
| -rw-r--r-- | src/cpu/intel/car/core2/cache_as_ram.S | 23 |
2 files changed, 21 insertions, 5 deletions
diff --git a/src/cpu/intel/car/cache_as_ram_symbols.inc b/src/cpu/intel/car/cache_as_ram_symbols.inc index 2d2f4bd0d831..0e5fdc33ee9b 100644 --- a/src/cpu/intel/car/cache_as_ram_symbols.inc +++ b/src/cpu/intel/car/cache_as_ram_symbols.inc @@ -16,6 +16,9 @@ rom_mtrr_base: car_mtrr_mask: .uintptr_t _car_mtrr_mask +car_mtrr_size: +.uintptr_t _car_mtrr_size + car_mtrr_start: .uintptr_t _car_mtrr_start diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 2c6720715411..f47ba5f05eab 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -7,6 +7,8 @@ .section .init .global bootblock_pre_c_entry +#include <cpu/intel/car/cache_as_ram_symbols.inc> + .code32 _cache_as_ram_setup: @@ -92,7 +94,7 @@ addrsize_set_high: /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr - movl $_car_mtrr_mask, %eax + movl car_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr @@ -119,8 +121,8 @@ addrsize_set_high: /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax - movl $_car_mtrr_start, %edi - movl $_car_mtrr_size, %ecx + movl car_mtrr_start, %edi + movl car_mtrr_size, %ecx shr $2, %ecx rep stosl @@ -134,12 +136,12 @@ addrsize_set_high: movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx movl $_program, %eax - andl $_xip_mtrr_mask, %eax + andl xip_mtrr_mask, %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $_xip_mtrr_mask, %eax + movl xip_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr @@ -157,6 +159,16 @@ addrsize_set_high: andl $0xfffffff0, %esp subl $4, %esp +#if ENV_X86_64 + + #include <cpu/x86/64bit/entry64.inc> + + movd %mm2, %rdi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi + movd %mm0, %rsi +#else /* push TSC and BIST to stack */ movd %mm0, %eax pushl %eax /* BIST */ @@ -164,6 +176,7 @@ addrsize_set_high: pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif before_c_entry: post_code(0x29) |