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| author | Patrick Georgi <pgeorgi@google.com> | 2021-01-12 15:09:57 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-14 16:53:06 +0000 |
| commit | d6eb72c87eb569000df62456c187329ee4967dc1 (patch) | |
| tree | fa8458b76763daaed1f3fbe55098e112492e3821 /src/cpu | |
| parent | 725596622d1362a192cc8203c5b331a7248454e3 (diff) | |
| download | coreboot-d6eb72c87eb569000df62456c187329ee4967dc1.tar.gz coreboot-d6eb72c87eb569000df62456c187329ee4967dc1.tar.bz2 coreboot-d6eb72c87eb569000df62456c187329ee4967dc1.zip | |
build system: Structure and serialize INTERMEDIATE
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying
the file in some way. When running them in parallel, coreboot.pre can be
read from and written to in parallel which can corrupt the result.
Add a function to create those rules that also adds existing
INTERMEDIATE targets to enforce an order (as established by evaluation
order of Makefile.inc files).
While at it, also add the addition to the PHONY target so we don't
forget it.
BUG=chromium:1154313, b:174585424
TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2
timeout and sercon) and saw that they were executed.
Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/fit/Makefile.inc | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/src/cpu/intel/fit/Makefile.inc b/src/cpu/intel/fit/Makefile.inc index 20483d8203e8..8d8f07d7504f 100644 --- a/src/cpu/intel/fit/Makefile.inc +++ b/src/cpu/intel/fit/Makefile.inc @@ -6,18 +6,14 @@ ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE),y) -PHONY+=add_mcu_fit -INTERMEDIATE+=add_mcu_fit -add_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL) +$(call add_intermediate, add_mcu_fit, $(obj)/coreboot.pre $(IFITTOOL)) @printf " UPDATE-FIT Microcode\n" $(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT # Second FIT in TOP_SWAP bootblock ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) -PHONY+=add_ts_mcu_fit -INTERMEDIATE+=add_ts_mcu_fit -add_ts_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL) +$(call add_intermediate, add_ts_mcu_fit, $(obj)/coreboot.pre $(IFITTOOL)) @printf " UPDATE-FIT Top Swap: Microcode\n" ifneq ($(FIT_ENTRY),) $(IFITTOOL) -f $< -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT |