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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-01-13 16:45:07 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-16 20:19:07 +0000 |
| commit | 8c93feda7f6cf7bfd90ecfa55e8bc73872c62f81 (patch) | |
| tree | 7752a914c6e4da6d1ad41a6aad4bf5b5105846db /src/device/Kconfig | |
| parent | 53c2250dbf6d21d9083ca2b32e21ffcc2be6b3f1 (diff) | |
| download | coreboot-8c93feda7f6cf7bfd90ecfa55e8bc73872c62f81.tar.gz coreboot-8c93feda7f6cf7bfd90ecfa55e8bc73872c62f81.tar.bz2 coreboot-8c93feda7f6cf7bfd90ecfa55e8bc73872c62f81.zip | |
device: Add support for PCIe Resizable BARs
Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can
indicates support for "Resizable BARs" via a PCIe extended capability.
When support this capability is indicated by the device, the size of
each BAR is determined in a different way than the normal "moving
bits" method. Instead, a pair of capability and control registers is
allocated in config space for each BAR, which can be used to both
indicate the different sizes the device is capable of supporting for
the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and
to also inform the device of the size that the allocator actually
reserved for the MMIO range.
This patch adds a Kconfig for a mainboard to select if it knows that it
will have a device that requires this support during PCI enumeration.
If so, there is a corresponding Kconfig to indicate the maximum number
of bits of address space to hand out to devices this way (again, limited
by what devices can support and each individual system may want to
support, but just like above, this number can range from 20 to 63) If
the device can support more bits than this Kconfig, the resource request
is truncated to the number indicated by this Kconfig.
BUG=b:214443809
TEST=compile (device with this capability not available yet),
also verify that no changes are seen in resource allocation for
google/brya0 before and after this change.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/device/Kconfig')
| -rw-r--r-- | src/device/Kconfig | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/device/Kconfig b/src/device/Kconfig index cd8d8e987325..8471d5d00ebd 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -632,6 +632,35 @@ config PCIEXP_L1_SUB_STATE help Detect and enable ASPM on PCIe links. +config PCIEXP_SUPPORT_RESIZABLE_BARS + prompt "Support PCIe Resizable BARs" + bool + depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT) + default n + help + When enabled, this will check PCIe devices for Resizable BAR support, + and if found, will use this to discover the preferred BAR sizes of + the device in preference over the traditional moving bits method. The + amount of address space given out to devices in this manner (since + it can range up to 8 EB) can be limited with the + PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS Kconfig setting below. + +if PCIEXP_SUPPORT_RESIZABLE_BARS + +config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS + int "Bits of address space to give to Resizable BARs" + range 20 63 # 1 MiB - 8 EiB + default 29 # 512 MiB + help + This is the maximum number of bits of address space to allocate for + PCIe devices with resizable BARs. For instance, if a device requests + 30 bits of address space (1 GiB), but this field is set to 29, then + the device will only be allocated 29 bits worth of address space (512 + MiB). Valid values range from 20 (1 MiB) to 63 (8 EiB); these come + from the Resizable BAR portion of the PCIe spec (7.8.6). + +endif # PCIEXP_SUPPORT_RESIZABLE_BARS + config PCIEXP_HOTPLUG prompt "Enable PCIe Hotplug Support" bool |