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| author | Felix Held <felix-coreboot@felixheld.de> | 2024-01-11 22:26:18 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-01-16 22:59:55 +0000 |
| commit | 3b5b66d82954e026a91a1eff833fa7f652fed629 (patch) | |
| tree | c7ff2cb87807e204d6f9e04e1cae14516eae0801 /src/device/device_util.c | |
| parent | 090ea7ab8fceae54488620160aa95da4292d663f (diff) | |
| download | coreboot-3b5b66d82954e026a91a1eff833fa7f652fed629.tar.gz coreboot-3b5b66d82954e026a91a1eff833fa7f652fed629.tar.bz2 coreboot-3b5b66d82954e026a91a1eff833fa7f652fed629.zip | |
device: Add support for multiple PCI segment groups
Add initial support for multiple PCI segment groups. Instead of
modifying secondary in the bus struct introduce a new segment_group
struct element and keep existing common code.
Since all platforms currently only use 1 segment this is not a
functional change. On platforms that support more than 1 segment the
segment has to be set when creating the PCI domain.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/device/device_util.c')
| -rw-r--r-- | src/device/device_util.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/device/device_util.c b/src/device/device_util.c index b37d1d9bfc72..ac2d33cdb9ce 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -97,7 +97,7 @@ u32 dev_path_encode(const struct device *dev) case DEVICE_PATH_ROOT: break; case DEVICE_PATH_PCI: - ret |= dev->bus->secondary << 8 | dev->path.pci.devfn; + ret |= dev->bus->segment_group << 16 | dev->bus->secondary << 8 | dev->path.pci.devfn; break; case DEVICE_PATH_PNP: ret |= dev->path.pnp.port << 8 | dev->path.pnp.device; @@ -168,7 +168,8 @@ const char *dev_path(const struct device *dev) break; case DEVICE_PATH_PCI: snprintf(buffer, sizeof(buffer), - "PCI: %02x:%02x.%01x", + "PCI: %02x:%02x:%02x.%01x", + dev->bus->segment_group, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); @@ -525,7 +526,8 @@ void report_resource_stored(struct device *dev, const struct resource *resource, if (dev->link_list && (resource->flags & IORESOURCE_PCI_BRIDGE)) { snprintf(buf, sizeof(buf), - "bus %02x ", dev->link_list->secondary); + "seg %02x bus %02x ", dev->link_list->segment_group, + dev->link_list->secondary); } printk(BIOS_DEBUG, "%s %02lx <- [0x%016llx - 0x%016llx] size 0x%08llx " "gran 0x%02x %s%s%s\n", dev_path(dev), resource->index, @@ -982,5 +984,5 @@ bool is_enabled_pci(const struct device *pci) bool is_pci_dev_on_bus(const struct device *pci, unsigned int bus) { - return is_pci(pci) && pci->bus->secondary == bus; + return is_pci(pci) && pci->bus->segment_group == 0 && pci->bus->secondary == bus; } |