x86: Separate CPU and SoC physical address size

The physical address size of the System-on-Chip (SoC) can be different
from the CPU physical address size. These two different physical
address sizes should be used for settings of their respective field.

For instance, the physical address size related to the CPU should be
used for MTRR programming while the physical address size of the SoC
should be used for MMIO resource allocation.

Typically, on Meteor Lake, the CPUs physical address size is 46 if TME
is disabled and 42 if TME is enabled but Meteor Lake SoC physical
address size is always 42. As a result, MTRRs should reflect the TME
status while coreboot MMIO resource allocator should always use
42 bits.

This commit introduces `SOC_PHYSICAL_ADDRESS_WIDTH' Kconfig to set the
physical address size of the SoC for those SoCs.

BUG=b:314886709
TEST=MTRR are aligned between coreboot and FSP

Change-Id: Icb76242718581357e5c62c2465690cf489cb1375
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79665
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 1 insertions, 1 deletions

diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 21b43529d7f8..b356c2695bb6 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -578,7 +578,7 @@ void pci_domain_read_resources(struct device *dev)
 	/* Initialize 64-bit memory resource constraints above 4G. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(2, 0));
 	res->base  = 4ULL * GiB;
-	res->limit = (1ULL << cpu_phys_address_size()) - 1;
+	res->limit = (1ULL << soc_phys_address_size()) - 1;
 	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 		     IORESOURCE_ASSIGNED;
 }