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| author | Nico Huber <nico.h@gmx.de> | 2022-02-25 14:25:57 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-28 13:28:12 +0000 |
| commit | f514b8ae82ab73dfc2a7e57f75861c6d9ee2a7eb (patch) | |
| tree | 945df3e2ebd3ded0a6dbf1c60853f64e78c5f77e /src/device/pci_device.c | |
| parent | e6ab52e289c0cc9b1efcab7fa345264ffa9ed144 (diff) | |
| download | coreboot-f514b8ae82ab73dfc2a7e57f75861c6d9ee2a7eb.tar.gz coreboot-f514b8ae82ab73dfc2a7e57f75861c6d9ee2a7eb.tar.bz2 coreboot-f514b8ae82ab73dfc2a7e57f75861c6d9ee2a7eb.zip | |
device/pci_device: Fix PCIe bridge detection
PCI bus 0 is not below any PCI device. In case of pci_domain_scan_bus(),
it's our virtual `domain` device.
Expecting a PCI device above bus 0 resulted in undefined behavior for
all boards with PCI. Only boards with a PCI device 00:00.0 that looked
like a PCIe bridge showed issues, though (e.g. OCP/DeltaLake).
Change-Id: I1fd68b9dc0d2e388ec2bbba4adbadd33e14f0171
Signed-off-by: Nico Huber <nico.h@gmx.de>
Fixes: commit 777ffff442 (device/pci_device.c: Scan only one device for PCIe)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62376
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device/pci_device.c')
| -rw-r--r-- | src/device/pci_device.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 2acc51780416..82494b98300c 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1352,6 +1352,9 @@ static bool pci_bus_only_one_child(struct bus *bus) if (!bridge) return false; + if (bridge->path.type != DEVICE_PATH_PCI) + return false; + pcie_pos = pci_find_capability(bridge, PCI_CAP_ID_PCIE); if (!pcie_pos) return false; |