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| author | Furquan Shaikh <furquan@google.com> | 2020-05-14 14:52:14 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-05-16 17:47:57 +0000 |
| commit | 563424e986edc1027d49c0efd151118a2e687c86 (patch) | |
| tree | 094a7b520ea8d71e0ea9e9ae377cb91b90df45a8 /src/device/pciexp_device.c | |
| parent | 72f06ca554e6f7b155a6b4e2b8ce57942288ac2c (diff) | |
| download | coreboot-563424e986edc1027d49c0efd151118a2e687c86.tar.gz coreboot-563424e986edc1027d49c0efd151118a2e687c86.tar.bz2 coreboot-563424e986edc1027d49c0efd151118a2e687c86.zip | |
Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports"
This reverts commit 2412924bc7646fc22b2cb1b9108413fa3e849082.
Reason for revert: Resource allocator patches need to be reverted
until the AMD chipsets can be fixed to handle the resource allocation
flow correctly.
BUG=b:149186922
Change-Id: Iea6db8cc0cb5a0e81d176ed3199c91dcd02d1859
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41411
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device/pciexp_device.c')
0 files changed, 0 insertions, 0 deletions