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| author | Nico Huber <nico.h@gmx.de> | 2022-08-05 14:50:06 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-17 19:09:05 +0000 |
| commit | 5f7cfb388e6d267cea8c435643373d248d037470 (patch) | |
| tree | 0481bd48c5b84c6efa3a1536c1d446009397d077 /src/device/pciexp_device.c | |
| parent | 077dc2eca2a1fbd105c04183ef8767f120f6fc12 (diff) | |
| download | coreboot-5f7cfb388e6d267cea8c435643373d248d037470.tar.gz coreboot-5f7cfb388e6d267cea8c435643373d248d037470.tar.bz2 coreboot-5f7cfb388e6d267cea8c435643373d248d037470.zip | |
pciexp_device: Fix offset handling for extended capabilities
The PCIe spec explicitly states that the bottom-two bits of the next
offset are reserved for future use and should be masked. We can also
change the loop condition to avoid wrong offsets below 0x100 (exten-
ded capabilities always reside in the extended config space).
The whole patch series was tested on Google Samus and keeps the L1ss
configuration of the WiFi device in tact.
Change-Id: I0b622a0ce0a4a1127d266226ade0ec1e66e9fb79
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66459
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device/pciexp_device.c')
| -rw-r--r-- | src/device/pciexp_device.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 05ac4fc58807..449315bb295d 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -16,7 +16,7 @@ static unsigned int ext_cap_id(unsigned int cap) static unsigned int ext_cap_next_offset(unsigned int cap) { - return cap >> 20; + return cap >> 20 & 0xffc; } static unsigned int find_ext_cap_offset(const struct device *dev, unsigned int cap_id, @@ -24,7 +24,7 @@ static unsigned int find_ext_cap_offset(const struct device *dev, unsigned int c { unsigned int this_cap_offset = offset; - while (this_cap_offset != 0) { + while (this_cap_offset >= PCIE_EXT_CAP_OFFSET) { const unsigned int this_cap = pci_read_config32(dev, this_cap_offset); /* Bail out when this request is unsupported */ |