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| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2021-02-22 09:53:43 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-07-13 14:30:07 +0000 |
| commit | 91a1276d532bb94bfa1ed0d50fbc71de67776f2d (patch) | |
| tree | baae162c542922031dc0f0fa4e1e7ade140989c1 /src/drivers/camera | |
| parent | 82225b81f8e4e07268e229e51863ecc706eb9b98 (diff) | |
| download | coreboot-91a1276d532bb94bfa1ed0d50fbc71de67776f2d.tar.gz coreboot-91a1276d532bb94bfa1ed0d50fbc71de67776f2d.tar.bz2 coreboot-91a1276d532bb94bfa1ed0d50fbc71de67776f2d.zip | |
soc/intel/alderlake: Implement WA for DDR5 DIMM modules
The coreboot SMBus driver requires additional changes to accomodate
the DDR5 EEPROM read which has resulted in a broken code flow for boot.
This CL serves as a temp WA to let FSP perform the SPD read for DDR5
and pass SPD addresses to FSP UPD array.
BUG=b:180458099
TEST=Build and boot DDR5 adlrvp to OS
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50996
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/camera')
0 files changed, 0 insertions, 0 deletions