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| author | Angel Pons <th3fanbus@gmail.com> | 2021-05-26 15:32:53 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-27 15:40:22 +0000 |
| commit | a30641295a1907aeef73f3a38677ef8ec94b6f85 (patch) | |
| tree | 265b488b49dbe3a92432f197a9a197f46d6d432b /src/drivers/intel/fsp1_1/ramstage.c | |
| parent | eca0d70c98b546455371f2103cfc78fc5028fd47 (diff) | |
| download | coreboot-a30641295a1907aeef73f3a38677ef8ec94b6f85.tar.gz coreboot-a30641295a1907aeef73f3a38677ef8ec94b6f85.tar.bz2 coreboot-a30641295a1907aeef73f3a38677ef8ec94b6f85.zip | |
drivers/intel/fsp1_1: Drop weak function definition
The only FSP 1.1 platform is Braswell, which has a non-weak definition
for the `soc_silicon_init_params` function. This changes the resulting
BUILD_TIMELESS=1 coreboot image for Facebook fbg1701, for some reason.
Change-Id: I2a1b51cda9eb21d7af8372c16a43195a4bdd9543
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/drivers/intel/fsp1_1/ramstage.c')
| -rw-r--r-- | src/drivers/intel/fsp1_1/ramstage.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 597e88646567..3ae473bd0443 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -172,8 +172,3 @@ __weak void mainboard_silicon_init_params( SILICON_INIT_UPD *params) { } - -/* Initialize the UPD parameters for SiliconInit */ -__weak void soc_silicon_init_params(SILICON_INIT_UPD *params) -{ -} |