drivers/intel/fsp2_0/include/fsp: fix fsp_header

This patch aligns fsp_header with the Intel specification 2.0 and 2.3.
The main impetus for this change is to make the fsp_info_header fully
accessible in soc/vendor code. Here items such as image_revision can be
checked.

TEST=verify image revision output in the coreboot serial log.
     compare to FSP version shown in serial debug output.
     verify Google Guybrush machine boots into OS.

Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: Ibf50f16b5e9793d946a95970fcdabc4c07289646
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

1 files changed, 14 insertions, 7 deletions

diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c
index 4c8085ed65ef..d209e4ce2d1a 100644
--- a/src/drivers/intel/fsp2_0/header_display.c
+++ b/src/drivers/intel/fsp2_0/header_display.c
@@ -8,13 +8,14 @@ void fsp_print_header_info(const struct fsp_header *hdr)
 	union fsp_revision revision;
 	union extended_fsp_revision ext_revision;
 	ext_revision.val = 0;
+	int i;
 
 	/* For FSP 2.3 and later use extended image revision field present in header
 	 * for build number and revision calculation */
 	if (CONFIG(PLATFORM_USES_FSP2_3))
-		ext_revision.val = hdr->extended_fsp_revision;
+		ext_revision.val = hdr->extended_image_revision;
 
-	revision.val = hdr->fsp_revision;
+	revision.val = hdr->image_revision;
 	printk(BIOS_SPEW, "Spec version: v%u.%u\n", (hdr->spec_version >> 4),
 						     hdr->spec_version & 0xf);
 	printk(BIOS_SPEW, "Revision: %u.%u.%u, Build Number %u\n",
@@ -25,22 +26,28 @@ void fsp_print_header_info(const struct fsp_header *hdr)
 	printk(BIOS_SPEW, "Type: %s/%s\n",
 			(hdr->component_attribute & 1) ? "release" : "debug",
 			(hdr->component_attribute & 2) ? "official" : "test");
-	printk(BIOS_SPEW, "image ID: %s, base 0x%zx + 0x%zx\n",
-		hdr->image_id, (size_t)hdr->image_base, (size_t)hdr->image_size);
+
+	printk(BIOS_SPEW, "image ID: ");
+	for (i = 0; i < FSP_IMAGE_ID_LENGTH; i++)
+		printk(BIOS_SPEW, "%c", hdr->image_id[i]);
+	printk(BIOS_SPEW, "\n");
+
+	printk(BIOS_SPEW, "	base 0x%zx + 0x%zx\n",
+		(size_t)hdr->image_base, (size_t)hdr->image_size);
 	printk(BIOS_SPEW, "\tConfig region        0x%zx + 0x%zx\n",
 		(size_t)hdr->cfg_region_offset, (size_t)hdr->cfg_region_size);
 
 	if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) {
 		printk(BIOS_SPEW, "\tMemory init offset   0x%zx\n",
-		       (size_t)hdr->memory_init_entry_offset);
+		       (size_t)hdr->fsp_memory_init_entry_offset);
 	}
 
 	if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) {
 		printk(BIOS_SPEW, "\tSilicon init offset  0x%zx\n",
-		       (size_t)hdr->silicon_init_entry_offset);
+		       (size_t)hdr->fsp_silicon_init_entry_offset);
 		if (CONFIG(PLATFORM_USES_FSP2_2))
 			printk(BIOS_SPEW, "\tMultiPhaseSiInit offset  0x%zx\n",
-			       (size_t)hdr->multi_phase_si_init_entry_offset);
+			       (size_t)hdr->fsp_multi_phase_si_init_entry_offset);
 		printk(BIOS_SPEW, "\tNotify phase offset  0x%zx\n",
 		       (size_t)hdr->notify_phase_entry_offset);
 	}