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| author | Raul E Rangel <rrangel@chromium.org> | 2021-11-05 10:29:24 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-11-08 20:20:01 +0000 |
| commit | 159284606a761ea7f5574d9e8eb5cde20a1300ef (patch) | |
| tree | ff913b3fd70eddc92d544026a4504d9de5d82208 /src/drivers/intel/fsp2_0/include/fsp/api.h | |
| parent | 82897c9c4f15880a7efa21c4e11a0929975384a1 (diff) | |
| download | coreboot-159284606a761ea7f5574d9e8eb5cde20a1300ef.tar.gz coreboot-159284606a761ea7f5574d9e8eb5cde20a1300ef.tar.bz2 coreboot-159284606a761ea7f5574d9e8eb5cde20a1300ef.zip | |
drivers/intel/fsp2_0: Add preload_fspm and preload_fsps
In the non-XIP world, FSP is normally memmapped and then decompressed.
The AMD SPI DMA controller can actually read faster than mmap. So by
reading the contents into a buffer and then decompressing we reduce boot
time.
BUG=b:179699789
TEST=Boot guybrush and see 30ms reduction in boot time
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I28d7530ae9e50f743e3d6c86a5a29b1fa85cacb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/drivers/intel/fsp2_0/include/fsp/api.h')
| -rw-r--r-- | src/drivers/intel/fsp2_0/include/fsp/api.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 68b84703cad6..c035452e0540 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -32,7 +32,9 @@ enum fsp_notify_phase { }; /* Main FSP stages */ +void preload_fspm(void); void fsp_memory_init(bool s3wake); +void preload_fsps(void); void fsp_silicon_init(void); /* |