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| author | Brandon Breitenstein <brandon.breitenstein@intel.com> | 2016-07-27 17:34:45 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-02 18:12:24 +0200 |
| commit | c31ba0ef529ef571ea839572f2c701a871cb33d7 (patch) | |
| tree | 32b38059ace1ce791edabe57ddd8f4056776258c /src/drivers/intel/fsp2_0/include/fsp/api.h | |
| parent | e96543e1fa3510a735d6de391b89ac350f56d287 (diff) | |
| download | coreboot-c31ba0ef529ef571ea839572f2c701a871cb33d7.tar.gz coreboot-c31ba0ef529ef571ea839572f2c701a871cb33d7.tar.bz2 coreboot-c31ba0ef529ef571ea839572f2c701a871cb33d7.zip | |
drivers/intel/fsp2_0: Make FSP Headers Consumable out of Box
The following patch is based off of the UEFI 2.6 patch. The FSP header files
are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated
since the other headers expect it to be in the root of an includable directory.
Any struct defines were removed since they are defined in the headers and no
longer need to be explicity declared as struct with the UEFI 2.6 includes.
BUG=chrome-os-partner:54100
BRANCH=none
TEST=confirmed coreboot builds successfully
Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>#
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16308
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/intel/fsp2_0/include/fsp/api.h')
| -rw-r--r-- | src/drivers/intel/fsp2_0/include/fsp/api.h | 32 |
1 files changed, 4 insertions, 28 deletions
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index a6228f2264f1..b0436e829053 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -14,33 +14,9 @@ #define _FSP2_0_API_H_ #include <stddef.h> -#include <fsp/info_header.h> -#include <soc/fsp/FspmUpd.h> -#include <soc/fsp/FspsUpd.h> +#include <fsp/soc_binding.h> -enum fsp_status { - FSP_SUCCESS = 0x00000000, - FSP_STATUS_RESET_REQUIRED_COLD = 0x40000001, - FSP_STATUS_RESET_REQUIRED_WARM = 0x40000002, - FSP_STATUS_RESET_REQUIRED_3 = 0x40000003, - FSP_STATUS_RESET_REQUIRED_4 = 0x40000004, - FSP_STATUS_RESET_REQUIRED_5 = 0x40000005, - FSP_STATUS_RESET_REQUIRED_6 = 0x40000006, - FSP_STATUS_RESET_REQUIRED_7 = 0x40000007, - FSP_STATUS_RESET_REQUIRED_8 = 0x40000008, - FSP_INVALID_PARAMETER = 0x80000002, - FSP_UNSUPPORTED = 0x80000003, - FSP_NOT_READY = 0x80000006, - FSP_DEVICE_ERROR = 0x80000007, - FSP_OUT_OF_RESOURCES = 0x80000009, - FSP_VOLUME_CORRUPTED = 0x8000000a, - FSP_NOT_FOUND = 0x8000000a, - FSP_TIMEOUT = 0x80000012, - FSP_ABORTED = 0x80000015, - FSP_INCOMPATIBLE_VERSION = 0x80000010, - FSP_SECURITY_VIOLATION = 0x8000001a, - FSP_CRC_ERROR = 0x8000001b, -}; +#define FSP_SUCCESS EFI_SUCCESS enum fsp_boot_mode { FSP_BOOT_WITH_FULL_CONFIGURATION = 0x00, @@ -64,8 +40,8 @@ void fsp_memory_init(bool s3wake); void fsp_silicon_init(void); /* Callbacks for updating stage-specific parameters */ -void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd); -void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd); +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd); +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd); /* Callback after processing FSP notify */ void platform_fsp_notify_status(enum fsp_notify_phase phase); |