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| author | Subrata Banik <subrata.banik@intel.com> | 2020-05-26 18:26:54 +0530 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2020-06-14 17:48:31 +0000 |
| commit | 33d9c4ad7e9e8048e90858edd8e0212e23a0ac8e (patch) | |
| tree | d0c401d3d2c099bf1a307547bc53dfafa3b686c2 /src/drivers/intel/fsp2_0/util.c | |
| parent | f7841d03e2580c666f544e7bb625b1df0ed298a4 (diff) | |
| download | coreboot-33d9c4ad7e9e8048e90858edd8e0212e23a0ac8e.tar.gz coreboot-33d9c4ad7e9e8048e90858edd8e0212e23a0ac8e.tar.bz2 coreboot-33d9c4ad7e9e8048e90858edd8e0212e23a0ac8e.zip | |
drivers/intel/fsp2_0: Add FSP 2.2 specific support
• Based on FSP EAS v2.1 – Backward compatibility is retained.
• Add multi-phase silicon initialization to increase the modularity of the
FspSiliconInit() API.
• Add FspMultiPhaseSiInit() API
• FSP_INFO_HEADER changes
o Added FspMultiPhaseSiInitEntryOffset
• Add FSPS_ARCH_UPD
o Added EnableMultiPhaseSiliconInit, bootloaders designed for
FSP 2.0/2.1 can disable the FspMultiPhaseSiInit() API and
continue to use FspSiliconInit() without change.
FSP 2.2 Specification:
https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html
Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41728
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/intel/fsp2_0/util.c')
| -rw-r--r-- | src/drivers/intel/fsp2_0/util.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index a00b68462416..e8c587628e67 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -49,6 +49,8 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) hdr->notify_phase_entry_offset = read32(raw_hdr + 56); hdr->memory_init_entry_offset = read32(raw_hdr + 60); hdr->silicon_init_entry_offset = read32(raw_hdr + 68); + if (CONFIG(PLATFORM_USES_FSP2_2)) + hdr->multi_phase_si_init_entry_offset = read32(raw_hdr + 72); return CB_SUCCESS; } |