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| author | Bora Guvendik <bora.guvendik@intel.com> | 2016-05-09 17:18:26 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-06-09 20:25:58 +0200 |
| commit | de4b09fa26f37396ceaaa27d6ca8a038364f1e52 (patch) | |
| tree | ee009b291a3867951b244776480627095febab8d /src/drivers/intel | |
| parent | 1a718642ead0aa42561e4db30431066d53fdb57c (diff) | |
| download | coreboot-de4b09fa26f37396ceaaa27d6ca8a038364f1e52.tar.gz coreboot-de4b09fa26f37396ceaaa27d6ca8a038364f1e52.tar.bz2 coreboot-de4b09fa26f37396ceaaa27d6ca8a038364f1e52.zip | |
soc/intel/apollolake: Update FSP header files
Update autogenerated FSP 2.0 generic header files
based on FSP release 136_30.
Changes were made to avoid duplicating some of the
structs for every SoC.
BUG=chrome-os-partner:50765
TEST=Build coreboot
Change-Id: I6f3c9270fb67210d6ea87e17ccf52d203fa64b4b
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7145
Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7584
Reviewed-on: https://review.coreboot.org/15081
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/intel')
| -rw-r--r-- | src/drivers/intel/fsp2_0/include/fsp/upd.h | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h new file mode 100644 index 000000000000..004d91b9c604 --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP2_0_UPD_H_ +#define _FSP2_0_UPD_H_ + +struct FSP_UPD_HEADER { + /// + /// UPD Region Signature. This signature will be + /// "XXXXXX_T" for FSP-T + /// "XXXXXX_M" for FSP-M + /// "XXXXXX_S" for FSP-S + /// Where XXXXXX is an unique signature + /// + uint64_t Signature; + /// + /// Revision of the Data structure. For FSP v2.0 value is 1. + /// + uint8_t Revision; + uint8_t Reserved[23]; +} __attribute__((packed)); + +struct FSPM_ARCH_UPD { + /// + /// Revision of the structure. For FSP v2.0 value is 1. + /// + uint8_t Revision; + uint8_t Reserved[3]; + /// + /// Pointer to the non-volatile storage (NVS) data buffer. + /// If it is NULL it indicates the NVS data is not available. + /// + void *NvsBufferPtr; + /// + /// Pointer to the temporary stack base address to be + /// consumed inside FspMemoryInit() API. + /// + void *StackBase; + /// + /// Temporary stack size to be consumed inside + /// FspMemoryInit() API. + /// + uint32_t StackSize; + /// + /// Size of memory to be reserved by FSP below "top + /// of low usable memory" for bootloader usage. + /// + uint32_t BootLoaderTolumSize; + /// + /// Current boot mode. + /// + uint32_t BootMode; + uint8_t Reserved1[8]; +} __attribute__((packed)); + +#endif /* _FSP2_0_UPD_H_ */ |