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authorMartin Roth <martin@se-eng.com>2012-12-05 16:22:54 -0700
committerMarc Jones <marcj303@gmail.com>2012-12-12 22:34:16 +0100
commit3316cf2ff80f379b609115f375f73ef4b9e7d8f4 (patch)
tree451e03092e92a06782e4b058004e123b51c69e58 /src/drivers/spi/sst.c
parentcf5aaaf1d25429fa6270c7d91a3e072dcf989079 (diff)
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Claim the SPI bus before writes if the IMC ROM is present
The SB800 and Hudson now support adding the IMC ROM which runs from the same chip as coreboot. When the IMC is running, write or erase commands sent to the spi bus will fail, and the IMC will die. To fix this, we send a request to the IMC to stop fetching from the SPI rom while we write to it. This process (in one form or another) is required for writes to the SPI bus while the IMC is running. Because the IMC can take up to 500ms to respond every time we claim the bus, this patch tries to keep the number of times we need to do that to a minimum. We only need to claim the bus on writes, and using a counter for the semaphore allows us to call in once to claim the bus at the beginning of a number of transactions and it will stay claimed until we release it at the end of the transactions. Claim() - takes up to 500ms hit claim() - no delay erase() release() claim() - no delay write() release() Release() Change-Id: I4e003c5122a2ed47abce57ab8b92dee6aa4713ed Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1976 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/drivers/spi/sst.c')
-rw-r--r--src/drivers/spi/sst.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c
index 2609591723b2..8cf3f964fd41 100644
--- a/src/drivers/spi/sst.c
+++ b/src/drivers/spi/sst.c
@@ -153,6 +153,7 @@ sst_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf)
int ret;
u8 cmd[4];
+ flash->spi->rw = SPI_WRITE_FLAG;
ret = spi_claim_bus(flash->spi);
if (ret) {
printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n");