drivers/tpm/cr50: Add TPM IRQ timeout Kconfig option

The current 10ms timeout for SPI TPM IRQ is not enough for platforms
using ti50 (such as corsola). Therefore, introduce a new Kconfig option
'GOOGLE_TPM_IRQ_TIMEOUT_MS'.

For platforms using cr50, we need to support legacy pre-ready-IRQ cr50
factory images during the initial boot, so the timeout remains 100ms for
I2C TPM and 10ms for SPI TPM. For all the other platforms using ti50,
the default timeout is increased to 750ms, as suggested by the ti50 team
(apronin@google.com).

BUG=b:232327704
TEST=emerge-corsola coreboot
BRANCH=none

Change-Id: I8dbb919e4a421a99a994913613a33738a49f5956
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

1 files changed, 8 insertions, 20 deletions

diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c
index 8625a7921bad..5645e57d8299 100644
--- a/src/drivers/spi/tpm/tpm.c
+++ b/src/drivers/spi/tpm/tpm.c
@@ -15,6 +15,7 @@
 #include <commonlib/endian.h>
 #include <console/console.h>
 #include <delay.h>
+#include <drivers/tpm/cr50.h>
 #include <endian.h>
 #include <security/tpm/tis.h>
 #include <string.h>
@@ -63,6 +64,9 @@ __weak int tis_plat_irq_status(void)
 {
 	static int warning_displayed;
 
+	if (!CONFIG(TPM_GOOGLE))
+		dead_code();
+
 	if (!warning_displayed) {
 		printk(BIOS_WARNING, "%s() not implemented, wasting 10ms to wait on"
 		       " Cr50!\n", __func__);
@@ -74,23 +78,6 @@ __weak int tis_plat_irq_status(void)
 }
 
 /*
- * TPM may trigger a IRQ after finish processing previous transfer.
- * Waiting for this IRQ to sync TPM status.
- */
-static enum cb_err tpm_sync(void)
-{
-	struct stopwatch sw;
-
-	stopwatch_init_msecs_expire(&sw, 10);
-	while (!tis_plat_irq_status()) {
-		if (stopwatch_expired(&sw))
-			return CB_ERR;
-	}
-
-	return CB_SUCCESS;
-}
-
-/*
  * Each TPM2 SPI transaction starts the same: CS is asserted, the 4 byte
  * header is sent to the TPM, the master waits til TPM is ready to continue.
  */
@@ -113,7 +100,7 @@ static enum cb_err start_transaction(int read_write, size_t bytes, unsigned int
 
 		/* Wait for TPM to finish previous transaction if needed */
 		if (tpm_sync_needed) {
-			if (tpm_sync() != CB_SUCCESS)
+			if (cr50_wait_tpm_ready() != CB_SUCCESS)
 				printk(BIOS_ERR, "Timeout waiting for TPM IRQ!\n");
 
 			/*
@@ -431,8 +418,9 @@ int tpm2_init(struct spi_slave *spi_if)
 
 	memcpy(&spi_slave, spi_if, sizeof(*spi_if));
 
-	/* clear any pending IRQs */
-	tis_plat_irq_status();
+	/* Clear any pending IRQs. */
+	if (CONFIG(TPM_GOOGLE))
+		tis_plat_irq_status();
 
 	/*
 	 * 150 ms should be enough to synchronize with the TPM even under the