tpm: Refactor TPM Kconfig dimensions

Break TPM related Kconfig into the following dimensions:

TPM transport support:
config CRB_TPM
config I2C_TPM
config SPI_TPM
config MEMORY_MAPPED_TPM (new)

TPM brand, not defining any of these is valid, and result in "generic" support:
config TPM_ATMEL (new)
config TPM_GOOGLE (new)
config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE)
config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE)

What protocol the TPM chip supports:
config MAINBOARD_HAS_TPM1
config MAINBOARD_HAS_TPM2

What the user chooses to compile (restricted by the above):
config NO_TPM
config TPM1
config TPM2

The following Kconfigs will be replaced as indicated:
config TPM_CR50 -> TPM_GOOGLE
config MAINBOARD_HAS_CRB_TPM -> CRB_TPM
config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL
config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE
config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM
config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE

Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

3 files changed, 6 insertions, 22 deletions

diff --git a/src/drivers/spi/tpm/Kconfig b/src/drivers/spi/tpm/Kconfig
index 8c39a4a44a5d..7a55318bb046 100644
--- a/src/drivers/spi/tpm/Kconfig
+++ b/src/drivers/spi/tpm/Kconfig
@@ -12,17 +12,3 @@ config DRIVER_TPM_SPI_CHIP
 	int "Chip Select of the TPM chip on its SPI bus"
 	default 0
 	depends on SPI_TPM
-
-config MAINBOARD_HAS_SPI_TPM_CR50
-	bool
-	default n
-	select MAINBOARD_HAS_SPI_TPM
-	help
-	  Board has a CR50 SPI TPM
-
-config MAINBOARD_HAS_SPI_TPM
-	bool
-	default n
-	select SPI_TPM
-	help
-	  Board has SPI TPM support
diff --git a/src/drivers/spi/tpm/Makefile.inc b/src/drivers/spi/tpm/Makefile.inc
index 01d3b6641e9c..023479f0d018 100644
--- a/src/drivers/spi/tpm/Makefile.inc
+++ b/src/drivers/spi/tpm/Makefile.inc
@@ -1,5 +1,3 @@
-bootblock-$(CONFIG_SPI_TPM) += tis.c tpm.c
-verstage-$(CONFIG_SPI_TPM) += tis.c tpm.c
-romstage-$(CONFIG_SPI_TPM) += tis.c tpm.c
-ramstage-$(CONFIG_SPI_TPM) += tis.c tpm.c
-postcar-$(CONFIG_SPI_TPM) += tis.c tpm.c
+ifeq ($(CONFIG_TPM)$(CONFIG_SPI_TPM),yy)
+all-y += tis.c tpm.c
+endif
diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c
index 43fd933dbfa3..1462dd9f7fe4 100644
--- a/src/drivers/spi/tpm/tpm.c
+++ b/src/drivers/spi/tpm/tpm.c
@@ -104,7 +104,7 @@ static enum cb_err start_transaction(int read_write, size_t bytes, unsigned int
 	static int tpm_sync_needed;
 	static struct stopwatch wake_up_sw;
 
-	if (CONFIG(TPM_CR50)) {
+	if (CONFIG(TPM_GOOGLE)) {
 		/*
 		 * First Cr50 access in each coreboot stage where TPM is used will be
 		 * prepended by a wake up pulse on the CS line.
@@ -186,7 +186,7 @@ static enum cb_err start_transaction(int read_write, size_t bytes, unsigned int
 	 */
 
 	header_resp.body[3] = 0;
-	if (CONFIG(TPM_CR50))
+	if (CONFIG(TPM_GOOGLE))
 		ret = spi_xfer(&spi_slave, header.body, sizeof(header.body), NULL, 0);
 	else
 		ret = spi_xfer(&spi_slave, header.body, sizeof(header.body),
@@ -497,7 +497,7 @@ int tpm2_init(struct spi_slave *spi_if)
 	       tpm_info.vendor_id, tpm_info.device_id, tpm_info.revision);
 
 	/* Do some cr50-specific things here. */
-	if (CONFIG(TPM_CR50) && tpm_info.vendor_id == 0x1ae0) {
+	if (CONFIG(TPM_GOOGLE) && tpm_info.vendor_id == 0x1ae0) {
 		struct cr50_firmware_version ver;
 
 		if (tpm_first_access_this_boot()) {