diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-03-21 12:26:58 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-03-22 20:02:20 +0000 |
| commit | ec5a5cc2924f6724c9e58124d71d76c6ce21b6fa (patch) | |
| tree | f7b00f4f6e7ec1bbf9784c3c92c9106ba5117071 /src/drivers/tpm | |
| parent | 5a0ad11868686795e8a8af6dd576a7c3a7f26fd6 (diff) | |
| download | coreboot-ec5a5cc2924f6724c9e58124d71d76c6ce21b6fa.tar.gz coreboot-ec5a5cc2924f6724c9e58124d71d76c6ce21b6fa.tar.bz2 coreboot-ec5a5cc2924f6724c9e58124d71d76c6ce21b6fa.zip | |
drivers/tpm/cr50: Use cr50_get_firmware_version in get_board_cfg
cr50_get_board_cfg() may be called in ramstage for some mainboards in
order to determine the BOARD_CFG register's value. The code was
written assuming that the firmware version was already retrieved, but
for boards calling this in ramstage, this is not the case. Therefore,
instead of using the cached cr50_firmware_version (which is all 0s in
ramstage at that time), use the cr50_get_firmware_version function
instead.
BUG=b:225206079, b:220685274
BRANCH=firmware-brya-14505.B
TEST=boot on brya0 and see:
[INFO ] Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.6.93/cr50_v3.94
[INFO ] Enabling GPIO PM b/c CR50 has long IRQ pulse support
in the logs.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia6e5f4965a8852793d2f95e6eb21ea87860335a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/drivers/tpm')
| -rw-r--r-- | src/drivers/tpm/cr50.c | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/src/drivers/tpm/cr50.c b/src/drivers/tpm/cr50.c index f96e17450b7a..1d6c69196ff0 100644 --- a/src/drivers/tpm/cr50.c +++ b/src/drivers/tpm/cr50.c @@ -13,8 +13,6 @@ (CONFIG(CR50_USE_LONG_INTERRUPT_PULSES) \ ? CR50_BOARD_CFG_100US_READY_PULSE : 0) -static struct cr50_firmware_version cr50_firmware_version; - enum cr50_register { CR50_FW_VER_REG, CR50_BOARD_CFG_REG, @@ -74,9 +72,13 @@ static bool cr50_fw_supports_board_cfg(struct cr50_firmware_version *version) */ static uint32_t cr50_get_board_cfg(void) { + struct cr50_firmware_version ver; uint32_t value; - if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) + if (cr50_get_firmware_version(&ver) != CB_SUCCESS) + return 0; + + if (!cr50_fw_supports_board_cfg(&ver)) return 0; const enum cb_err ret = tis_vendor_read(get_reg_addr(CR50_BOARD_CFG_REG), &value, @@ -94,10 +96,14 @@ static uint32_t cr50_get_board_cfg(void) */ enum cb_err cr50_set_board_cfg(void) { - uint32_t value; + struct cr50_firmware_version ver; enum cb_err ret; + uint32_t value; + + if (cr50_get_firmware_version(&ver) != CB_SUCCESS) + return CB_ERR; - if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) + if (!cr50_fw_supports_board_cfg(&ver)) return CB_ERR; /* Set the CR50_BOARD_CFG register, for e.g. asking cr50 to use longer ready pulses. */ @@ -167,6 +173,8 @@ static enum cb_err cr50_parse_fw_version(const char *version_str, enum cb_err cr50_get_firmware_version(struct cr50_firmware_version *version) { + static struct cr50_firmware_version cr50_firmware_version; + if (cr50_firmware_version.epoch || cr50_firmware_version.major || cr50_firmware_version.minor) goto success; |