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author | Nico Huber <nico.h@gmx.de> | 2019-02-09 13:13:45 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-11 12:23:54 +0000 |
commit | 0d25e5ac670d32f61e159cc6a2e9a68cd524d6a6 (patch) | |
tree | 6677ede2ca203e65ae5aa622d0f186394bccc570 /src/drivers | |
parent | f14445c145776877d140a17548b094467303e77e (diff) | |
download | coreboot-0d25e5ac670d32f61e159cc6a2e9a68cd524d6a6.tar.gz coreboot-0d25e5ac670d32f61e159cc6a2e9a68cd524d6a6.tar.bz2 coreboot-0d25e5ac670d32f61e159cc6a2e9a68cd524d6a6.zip |
soc/intel/fsp_broadwell_de: Move FSP_DEBUG_LEVEL option here
It is not mentioned in the FSP spec and doesn't seem to be implemented
for any other FSP than the Broadwell-DE one.
Change-Id: I87c758204f1aabf13f47de19fd87c6e1ed67258e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/drivers')
-rw-r--r-- | src/drivers/intel/fsp1_0/Kconfig | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index b2338aa123a5..4ce528fb77de 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -34,17 +34,6 @@ config DCACHE_RAM_SIZE hex default 0x4000 -config FSP_1_0_DEBUG_LEVEL - int "FSP debug level (0-3)" - default 0 - range 0 3 - help - Select the debug level, where: - 0: DISABLED - 1: MINIMUM - 2: NORMAL - 3: MAXIMUM - config FSP_HEADER_PATH string "Location of FSP headers" help |