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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-01-22 16:52:13 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-18 14:59:17 +0000 |
| commit | eb3cd856106dae68da4aae39f9954fb90770e8a2 (patch) | |
| tree | c824581892f358406184f02f355ad20c9adf6b1b /src/ec/google/chromeec/ec.h | |
| parent | 214fb9b511faaa59716a1b65a43438781f6237ef (diff) | |
| download | coreboot-eb3cd856106dae68da4aae39f9954fb90770e8a2.tar.gz coreboot-eb3cd856106dae68da4aae39f9954fb90770e8a2.tar.bz2 coreboot-eb3cd856106dae68da4aae39f9954fb90770e8a2.zip | |
ec/google/chromeec: Add SSDT generator for ChromeOS EC
Upcoming patches for the Linux kernel (5.6 ?) would like to consume
information about the USB PD ports that are attached to the device. This
information is obtained from the CrOS EC and exposed in the SSDT ACPI
table.
Also, the device enable for this PCI device is moved from ec_lpc.c to
a new file, ec_chip.c, where EC-related ACPI methods can live. It
still allows other code to call functions on device enable (so that
PnP enable for the LPC device still gets called).
BUG=b:146506369
BRANCH=none
TEST=Verify the SSDT contains the expected information
Change-Id: I729caecd64d9320fb02c0404c8315122f010970b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/ec/google/chromeec/ec.h')
| -rw-r--r-- | src/ec/google/chromeec/ec.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 5ce375e00b47..7341636819fe 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -18,6 +18,7 @@ #ifndef _EC_GOOGLE_CHROMEEC_EC_H #define _EC_GOOGLE_CHROMEEC_EC_H #include <types.h> +#include <device/device.h> #include "ec_commands.h" /* Fill in base and size of the IO port resources used. */ @@ -329,4 +330,26 @@ struct usb_pd_port_caps { int google_chromeec_get_pd_port_caps(int port, struct usb_pd_port_caps *port_caps); +#if CONFIG(HAVE_ACPI_TABLES) +/** + * Writes USB Type-C PD related information to the SSDT + * + * @param dev EC device + */ +void google_chromeec_fill_ssdt_generator(struct device *dev); + +/** + * Returns the ACPI name for the EC device. + * + * @param dev EC device + */ +const char *google_chromeec_acpi_name(const struct device *dev); + +#endif /* HAVE_ACPI_TABLES */ + +/* + * Allows bus-specific EC code to perform actions when the device is enabled. + */ +void google_ec_enable_extra(struct device *dev); + #endif /* _EC_GOOGLE_CHROMEEC_EC_H */ |