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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-05-04 23:00:06 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-08 16:00:54 +0000 |
| commit | 2d4112f76b004aa49ab8185cff4bd2313e01dff8 (patch) | |
| tree | aad6e068bade3c8f368a8d13348fdfa885b125d5 /src/include/acpi/acpigen.h | |
| parent | 98bb790286e980a6feab1451e8cc4b5be7fdf059 (diff) | |
| download | coreboot-2d4112f76b004aa49ab8185cff4bd2313e01dff8.tar.gz coreboot-2d4112f76b004aa49ab8185cff4bd2313e01dff8.tar.bz2 coreboot-2d4112f76b004aa49ab8185cff4bd2313e01dff8.zip | |
acpi/acpigen: add acpigen_write_BBN to generate base bus number method
Introduce acpigen_write_BBN to generate the ACPI method object that
returns the base bus number for a PCI(e) host bridge. When called, the
base_bus_number argument must be the first PCI bus number that got
assigned to the corresponding host bridge.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib67bf42b9c77c262d8a02d8f28ac5cb8482136b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Diffstat (limited to 'src/include/acpi/acpigen.h')
| -rw-r--r-- | src/include/acpi/acpigen.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index fc1d01b4e30d..1b60006656a1 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -435,6 +435,7 @@ void acpigen_write_PTC(uint8_t duty_width, uint8_t duty_offset, uint16_t p_cnt); void acpigen_write_PRW(u32 wake, u32 level); void acpigen_write_STA(uint8_t status); void acpigen_write_STA_ext(const char *namestring); +void acpigen_write_BBN(uint8_t base_bus_number); void acpigen_write_TPC(const char *gnvs_tpc_limit); void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control, u32 status); |