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| author | Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> | 2020-09-15 21:01:57 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-09-22 16:06:34 +0000 |
| commit | ca36aedb4e71a1b8e1738f5329ce20b6e83d174d (patch) | |
| tree | 534f0c9bb15c0ba1f25c5ff05fd9886732b910f4 /src/include/acpi/acpigen.h | |
| parent | ccbe5307d80c28953132a02dae97f0a984ffecbc (diff) | |
| download | coreboot-ca36aedb4e71a1b8e1738f5329ce20b6e83d174d.tar.gz coreboot-ca36aedb4e71a1b8e1738f5329ce20b6e83d174d.tar.bz2 coreboot-ca36aedb4e71a1b8e1738f5329ce20b6e83d174d.zip | |
acpi: Add SSDT pstate helper functions
Add new generic helper functions for PSS, PCT, XPSS, objects.
BUG=b:155307433
TEST=Boot Morphius and dump SSDT. Confirm PSS and PCT objects appear
as expected and conform to ACPI_6_3_May16.pdf ACPI specification.
Check XPSS against Microsoft "Extended PSS ACPI Method Specification"
XPSS_spec.doc April 2, 2007.
BRANCH=Zork
Change-Id: I1ea218bcee33093481e82390550ff96d9d2cb8b5
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/include/acpi/acpigen.h')
| -rw-r--r-- | src/include/acpi/acpigen.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index e44926f576d1..c30f8449b62e 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -324,6 +324,7 @@ void acpigen_write_STA_ext(const char *namestring); void acpigen_write_TPC(const char *gnvs_tpc_limit); void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control, u32 status); +void acpigen_write_pss_object(const struct acpi_sw_pstate *pstate_values, size_t nentries); typedef enum { SW_ALL = 0xfc, SW_ANY = 0xfd, HW_ALL = 0xfe } PSD_coord; void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); void acpigen_write_CST_package_entry(acpi_cstate_t *cstate); @@ -331,6 +332,10 @@ void acpigen_write_CST_package(acpi_cstate_t *entry, int nentries); typedef enum { CSD_HW_ALL = 0xfe } CSD_coord; void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, u32 index); +void acpigen_write_pct_package(const acpi_addr_t *perf_ctrl, const acpi_addr_t *perf_sts); +void acpigen_write_xpss_package(const struct acpi_xpss_sw_pstate *pstate_value); +void acpigen_write_xpss_object(const struct acpi_xpss_sw_pstate *pstate_values, + size_t nentries); void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); void acpigen_write_processor_package(const char *name, unsigned int first_core, |