diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-15 05:58:42 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-16 09:28:42 +0000 |
| commit | 4de1a31cb04f0363b6d257d9de392cdfe8d5644c (patch) | |
| tree | 80a674e5d82d33c5e133d31676ab48bad409798e /src/include/acpi | |
| parent | cdd2f63947549e9b478f26942daf400cf4f246e6 (diff) | |
| download | coreboot-4de1a31cb04f0363b6d257d9de392cdfe8d5644c.tar.gz coreboot-4de1a31cb04f0363b6d257d9de392cdfe8d5644c.tar.bz2 coreboot-4de1a31cb04f0363b6d257d9de392cdfe8d5644c.zip | |
ACPI: Add acpi_reset_gnvs_for_wake()
With chipset_power_state filled in romstage CBMEM hooks and
GNVS allocated early in ramstage, GNVS wake source is now
also filled for normal boot path.
Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/include/acpi')
| -rw-r--r-- | src/include/acpi/acpi_gnvs.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/include/acpi/acpi_gnvs.h b/src/include/acpi/acpi_gnvs.h index 498743f8973d..86d68a4d31ef 100644 --- a/src/include/acpi/acpi_gnvs.h +++ b/src/include/acpi/acpi_gnvs.h @@ -5,12 +5,16 @@ #include <types.h> +struct global_nvs; + void acpi_create_gnvs(void); #if CONFIG(ACPI_SOC_NVS) void *acpi_get_gnvs(void); void *acpi_get_device_nvs(void); +int acpi_reset_gnvs_for_wake(struct global_nvs **gnvs); #else static inline void *acpi_get_gnvs(void) { return NULL; } +static inline int acpi_reset_gnvs_for_wake(struct global_nvs **gnvs) { return -1; } #endif void gnvs_assign_chromeos(void *gnvs_section); @@ -21,7 +25,6 @@ void gnvs_set_ecfw_rw(void); * Defined as weak in common acpi as gnvs structure definition is * chipset specific. */ -struct global_nvs; void soc_fill_gnvs(struct global_nvs *gnvs); void mainboard_fill_gnvs(struct global_nvs *gnvs); |