diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-11-22 14:53:57 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-12-03 14:17:51 +0100 |
| commit | fb509830085e379cee8eb9b5f619c34c249c9d77 (patch) | |
| tree | 6ef8091fb064c4485267082995ac858ee28cc477 /src/include/console | |
| parent | 590ac64d5571d8b85e0ddd65b25b8cda9354de15 (diff) | |
| download | coreboot-fb509830085e379cee8eb9b5f619c34c249c9d77.tar.gz coreboot-fb509830085e379cee8eb9b5f619c34c249c9d77.tar.bz2 coreboot-fb509830085e379cee8eb9b5f619c34c249c9d77.zip | |
intel/fsp: Add post codes for FSP phases
Add post codes for the various FSP phases and use them as appropriate
in FSP 1.0 and 1.1 implementations.
This will make it more consistent to debug FSP hangs and resets.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados and chell
Change-Id: I32f8dde80a0c6c117fe0fa48cdfe2f9a83b9dbdf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3b616ff3c9d8b6d05c8bfe7f456f5c189e523547
Original-Change-Id: I081745dcc45b3e9e066ade2227e675801d6f669a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313822
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12595
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/include/console')
| -rw-r--r-- | src/include/console/post_codes.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 44a3ef239a9b..e6d12430f1be 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -203,6 +203,48 @@ #define POST_BS_PAYLOAD_BOOT 0x7b /** + * \brief Before calling FSP TempRamInit + * + * Going to call into FSP binary for TempRamInit phase + */ +#define POST_FSP_TEMP_RAM_INIT 0x90 + +/** + * \brief Before calling FSP TempRamExit + * + * Going to call into FSP binary for TempRamExit phase + */ +#define POST_FSP_TEMP_RAM_EXIT 0x91 + +/** + * \brief Before calling FSP MemoryInit + * + * Going to call into FSP binary for MemoryInit phase + */ +#define POST_FSP_MEMORY_INIT 0x92 + +/** + * \brief Before calling FSP SiliconInit + * + * Going to call into FSP binary for SiliconInit phase + */ +#define POST_FSP_SILICON_INIT 0x93 + +/** + * \brief Before calling FSP Notify before resource allocation + * + * Going to call into FSP binary for Notify phase + */ +#define POST_FSP_NOTIFY_BEFORE_ENUMERATE 0x94 + +/** + * \brief Before calling FSP Notify before finalize + * + * Going to call into FSP binary for Notify phase + */ +#define POST_FSP_NOTIFY_BEFORE_FINALIZE 0x95 + +/** * \brief Entry into elf boot * * This POST code is called right before invoking jmp_to_elf_entry() |