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| author | Aaron Durbin <adurbin@chromium.org> | 2016-11-09 23:20:30 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-11-12 00:19:22 +0100 |
| commit | 2b3e0cdfc4ddefb85e779fa789ba21406a5f76a3 (patch) | |
| tree | f28ff6229c6b6378747fc11b122d0f4c48b89880 /src/include/cpu/x86/mtrr.h | |
| parent | 8b5d04e1abd1d7c3b9447385b043b0d902d22a54 (diff) | |
| download | coreboot-2b3e0cdfc4ddefb85e779fa789ba21406a5f76a3.tar.gz coreboot-2b3e0cdfc4ddefb85e779fa789ba21406a5f76a3.tar.bz2 coreboot-2b3e0cdfc4ddefb85e779fa789ba21406a5f76a3.zip | |
soc/intel/common/lpss_i2c: configure buses by rise/fall times
The default register count calculations are leading to higher
frequencies than expected. Provide an alternative method for
calculating the register counts by utilizing the rise and
fall times of the bus. If the rise time is supplied the
rise/fall time values are used, but the register overrides
take precedence over the rise/fall time calculation. This
allows platforms to choose whichever method works the best.
BUG=chrome-os-partner:58889
Change-Id: I7747613ce51d8151848acd916c09ae97bfc4b86a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17350
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/include/cpu/x86/mtrr.h')
0 files changed, 0 insertions, 0 deletions