diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-11-17 17:25:48 +0100 |
|---|---|---|
| committer | David Hendricks <david.hendricks@gmail.com> | 2023-02-06 00:22:46 +0000 |
| commit | 20d25779c8eab9e21668a18a6180d75775f4eaee (patch) | |
| tree | 521cf8f4f8c9a4be624c22ffac10cc0e85ebd445 /src/include/device/device.h | |
| parent | 306bd40939dfee091186d28e1668607bc144decb (diff) | |
| download | coreboot-20d25779c8eab9e21668a18a6180d75775f4eaee.tar.gz coreboot-20d25779c8eab9e21668a18a6180d75775f4eaee.tar.bz2 coreboot-20d25779c8eab9e21668a18a6180d75775f4eaee.zip | |
device/pci_device.c: Add way to limit max bus numbers
By default this limits PCI buses to CONFIG_MMCONF_BUS_NUMBER.
Some platforms have multiple PCI root busses (e.g. xeon_sp), where bus
numbers are limited. This provides a basic check. On some platforms it
looks like programming 0xff to the subordinate bus number confuses and
hangs the hardware.
Change-Id: I0582b156df1a5f76119a3687886c4d58f2d3ad6f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/include/device/device.h')
| -rw-r--r-- | src/include/device/device.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/include/device/device.h b/src/include/device/device.h index 8b1dde1109fb..b4b2d20e115f 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -85,7 +85,8 @@ struct bus { uint16_t bridge_cmd; /* Bridge command register */ unsigned char link_num; /* The index of this link */ uint16_t secondary; /* secondary bus number */ - uint16_t subordinate; /* max subordinate bus number */ + uint16_t subordinate; /* subordinate bus number */ + uint16_t max_subordinate; /* max subordinate bus number */ unsigned char cap; /* PCi capability offset */ uint32_t hcdn_reg; /* For HyperTransport link */ |