Change all clrsetbits_leXX() to clrsetbitsXX()

This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.

This patch was created by running

 sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'

across the codebase and cleaning up formatting a bit.

Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

1 files changed, 4 insertions, 4 deletions

diff --git a/src/include/device/mmio.h b/src/include/device/mmio.h
index 9c5e27cfd8f5..4007cff7c36a 100644
--- a/src/include/device/mmio.h
+++ b/src/include/device/mmio.h
@@ -120,10 +120,10 @@ static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo,
  *
  * These will be translated to:
  *
- *  clrsetbits_le32(&disp_regs.ctrl, 0x6, 0x4);
- *  clrsetbits_le32(&disp_regs.ctrl, 0x1, 0x0);
+ *  clrsetbits32(&disp_regs.ctrl, 0x6, 0x4);
+ *  clrsetbits32(&disp_regs.ctrl, 0x1, 0x0);
  *
- *  clrsetbits_le32(&disp_regs.ctrl, 0x7, 0x3);
+ *  clrsetbits32(&disp_regs.ctrl, 0x7, 0x3);
  *  write32(&disp_regs.ctrl, 0x3);
  *
  *  (read32(&reg) & 0x6) >> 1
@@ -187,7 +187,7 @@ static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo,
 	_BF_IMPL(_WRITE32_BITFIELDS_IMPL, addr, __VA_ARGS__)
 
 #define SET32_BITFIELDS(addr, ...) \
-	_BF_IMPL(clrsetbits_le32, addr, __VA_ARGS__)
+	_BF_IMPL(clrsetbits32, addr, __VA_ARGS__)
 
 #define EXTRACT_BITFIELD(value, name) \
 	(((value) & _BF_MASK(name, 0)) >> name##_BITFIELD_SHIFT)