diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-01-13 16:45:07 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-16 20:19:07 +0000 |
| commit | 8c93feda7f6cf7bfd90ecfa55e8bc73872c62f81 (patch) | |
| tree | 7752a914c6e4da6d1ad41a6aad4bf5b5105846db /src/include/device/pci_def.h | |
| parent | 53c2250dbf6d21d9083ca2b32e21ffcc2be6b3f1 (diff) | |
| download | coreboot-8c93feda7f6cf7bfd90ecfa55e8bc73872c62f81.tar.gz coreboot-8c93feda7f6cf7bfd90ecfa55e8bc73872c62f81.tar.bz2 coreboot-8c93feda7f6cf7bfd90ecfa55e8bc73872c62f81.zip | |
device: Add support for PCIe Resizable BARs
Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can
indicates support for "Resizable BARs" via a PCIe extended capability.
When support this capability is indicated by the device, the size of
each BAR is determined in a different way than the normal "moving
bits" method. Instead, a pair of capability and control registers is
allocated in config space for each BAR, which can be used to both
indicate the different sizes the device is capable of supporting for
the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and
to also inform the device of the size that the allocator actually
reserved for the MMIO range.
This patch adds a Kconfig for a mainboard to select if it knows that it
will have a device that requires this support during PCI enumeration.
If so, there is a corresponding Kconfig to indicate the maximum number
of bits of address space to hand out to devices this way (again, limited
by what devices can support and each individual system may want to
support, but just like above, this number can range from 20 to 63) If
the device can support more bits than this Kconfig, the resource request
is truncated to the number indicated by this Kconfig.
BUG=b:214443809
TEST=compile (device with this capability not available yet),
also verify that no changes are seen in resource allocation for
google/brya0 before and after this change.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/include/device/pci_def.h')
| -rw-r--r-- | src/include/device/pci_def.h | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 06114363f624..1c4a3e76efdc 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -460,10 +460,11 @@ #define PCI_EXT_CAP_ID_PWR 4 /* Extended Capability lists*/ -#define PCIE_EXT_CAP_OFFSET 0x100 -#define PCIE_EXT_CAP_AER_ID 0x0001 -#define PCIE_EXT_CAP_L1SS_ID 0x001E -#define PCIE_EXT_CAP_LTR_ID 0x0018 +#define PCIE_EXT_CAP_OFFSET 0x100 +#define PCIE_EXT_CAP_AER_ID 0x0001 +#define PCIE_EXT_CAP_L1SS_ID 0x001E +#define PCIE_EXT_CAP_LTR_ID 0x0018 +#define PCIE_EXT_CAP_RESIZABLE_BAR 0x0015 /* Advanced Error Reporting */ #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ @@ -527,6 +528,16 @@ #define PCI_LTR_MAX_SNOOP 4 #define PCI_LTR_MAX_NOSNOOP 6 +/* PCIe Resizable BARs */ +#define PCI_REBAR_CAP_OFFSET 0x4 +#define PCI_REBAR_CAP_SIZE_MASK 0xfffffff0 +#define PCI_REBAR_CTRL_OFFSET 0x8 +#define PCI_REBAR_CTRL_NBARS_MASK 0xe0 +#define PCI_REBAR_CTRL_NBARS_SHIFT 5 +#define PCI_REBAR_CTRL_IDX_MASK 0x07 +#define PCI_REBAR_CTRL_SIZE_MASK 0xffff0000 +#define PCI_REBAR_CTRL_SIZE_SHIFT 16 + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded |