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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-01-15 15:02:55 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-10 20:10:55 +0200 |
| commit | e0dae99b47faf6e750938bc52550128a4351f93e (patch) | |
| tree | 0f07e9152f3698e0bcec60e4fb2bfbed3595fe73 /src/include/device/pci_def.h | |
| parent | c05710f196e2ff20881a67adace949efc29d9f1f (diff) | |
| download | coreboot-e0dae99b47faf6e750938bc52550128a4351f93e.tar.gz coreboot-e0dae99b47faf6e750938bc52550128a4351f93e.tar.bz2 coreboot-e0dae99b47faf6e750938bc52550128a4351f93e.zip | |
PCI - Add interrupt disable bit definition
BRANCH=none
BUG=None
TEST=Build Braswell/Strago
Change-Id: I11a4c02af3b40edf2252b9e20298941b99f31d21
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 1629d7454a3d4adb8930d14849c41c9a711f4c9a
Original-Change-Id: Ie907637f7c823de681ef2e315e803dffc6ad33d3
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241081
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9487
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/include/device/pci_def.h')
| -rw-r--r-- | src/include/device/pci_def.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index c49e4ebf364f..ef3427b4e7dd 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -18,6 +18,7 @@ #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ +#define PCI_COMMAND_INT_DISABLE 0x400 /* Interrupt disable */ #define PCI_STATUS 0x06 /* 16 bits */ #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ |