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| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2022-07-04 20:43:47 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-07 23:59:37 +0000 |
| commit | 25c20753885fb183424b5d74445a3a8643fe2d28 (patch) | |
| tree | 416899c36df8f0fe833a08f41439e7c8ba6a0c09 /src/include/device/pci_ids.h | |
| parent | b858f2e5c9535a562cbcd90bc643d7aec9737ed6 (diff) | |
| download | coreboot-25c20753885fb183424b5d74445a3a8643fe2d28.tar.gz coreboot-25c20753885fb183424b5d74445a3a8643fe2d28.tar.bz2 coreboot-25c20753885fb183424b5d74445a3a8643fe2d28.zip | |
soc/intel/common/graphics: Add another Meteor Lake device ID
Add 0x7d55 as another ID for Meteor Lake graphics controllers.
TEST=Boot with MTL silicon to check coreboot log for DID2
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iea01f6d4f2469fc0eeac73a3f1c4b9af1f39463c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Diffstat (limited to 'src/include/device/pci_ids.h')
| -rw-r--r-- | src/include/device/pci_ids.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 429a89bb2c1a..ec48a120ec87 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4009,7 +4009,8 @@ #define PCI_DID_INTEL_ADL_N_GT3 0x46D2 #define PCI_DID_INTEL_MTL_M_GT2 0x7d40 #define PCI_DID_INTEL_MTL_P_GT2_1 0x7d50 -#define PCI_DID_INTEL_MTL_P_GT2_2 0x7d60 +#define PCI_DID_INTEL_MTL_P_GT2_2 0x7d55 +#define PCI_DID_INTEL_MTL_P_GT2_3 0x7d60 #define PCI_DID_INTEL_RPL_P_GT1 0xa720 #define PCI_DID_INTEL_RPL_P_GT2 0xa7a8 #define PCI_DID_INTEL_RPL_P_GT3 0xa7a0 |