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| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2021-05-13 11:34:14 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-14 09:03:01 +0000 |
| commit | 351f1e68c45f4f092399bff6a4673b0e8d1d6f50 (patch) | |
| tree | 7e4fb8828f9f838d35674324e46f825bee5eab00 /src/include/device/pci_ids.h | |
| parent | 6e97ac76f336baff4caf3b2a4cbb1f5df551c06f (diff) | |
| download | coreboot-351f1e68c45f4f092399bff6a4673b0e8d1d6f50.tar.gz coreboot-351f1e68c45f4f092399bff6a4673b0e8d1d6f50.tar.bz2 coreboot-351f1e68c45f4f092399bff6a4673b0e8d1d6f50.zip | |
soc/intel/alderlake: Update CPU and IGD Device IDs
Updated CPU ID and IGD ID for Alder Lake as per EDS.
TEST=Code compilation works and coreboot is able to boot and identify
new device Ids.
Change-Id: I2759a41a0db1eba5d159edfc89460992914fcc3c
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/include/device/pci_ids.h')
| -rw-r--r-- | src/include/device/pci_ids.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index a3ee558f7685..1a9aa35645e7 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3812,6 +3812,7 @@ #define PCI_DEVICE_ID_INTEL_ADL_GT1_8 0x4618 #define PCI_DEVICE_ID_INTEL_ADL_GT1_9 0x4619 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2 0x46a0 +#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_1 0x46b0 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680 #define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0 |