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| author | Subrata Banik <subratabanik@google.com> | 2022-05-23 13:47:50 +0530 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-06-03 15:28:12 +0000 |
| commit | 510a55d4eeaeb32047c17328ef238b55b89e7296 (patch) | |
| tree | b1aa5a4ca3983503f98fa3927fdb81dc117b0ad6 /src/include/device/pci_ids.h | |
| parent | c3bfbafda5c3241ff74ec1de3fbdc469af0e4ce0 (diff) | |
| download | coreboot-510a55d4eeaeb32047c17328ef238b55b89e7296.tar.gz coreboot-510a55d4eeaeb32047c17328ef238b55b89e7296.tar.bz2 coreboot-510a55d4eeaeb32047c17328ef238b55b89e7296.zip | |
drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driver
This patch removes the MTL CNVi DIDs macros from IA common code and is
added into the generic wifi driver.
As per Intel Connectivity Platform BIOS Guide, Connectivity Controller
IP for MTL-P is `Magnetar` and supported CRF is `Typhoon Peak 2`.
Previously Garfield Peak DIDs for Alder Lake SoC also added similarly
to generic wifi drivers.
BUG=b:224325352
TEST=Able to build and boot on MTL emulator.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib98762749c71f63df3e8d03be910539469359c68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/include/device/pci_ids.h')
| -rw-r--r-- | src/include/device/pci_ids.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ddc055fdf23c..b34158fe49d2 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4420,6 +4420,10 @@ #define PCI_DID_GrP_6SERIES_1_WIFI 0x51f0 #define PCI_DID_GrP_6SERIES_2_WIFI 0x7af0 #define PCI_DID_GrP_6SERIES_3_WIFI 0x51f1 +#define PCI_DID_TyP2_6SERIES_1_WIFI 0x7e40 +#define PCI_DID_TyP2_6SERIES_2_WIFI 0x7e41 +#define PCI_DID_TyP2_6SERIES_3_WIFI 0x7e42 +#define PCI_DID_TyP2_6SERIES_4_WIFI 0x7e43 #define PCI_DID_INTEL_TGL_IPU 0x9a19 #define PCI_DID_INTEL_TGL_H_IPU 0x9a39 @@ -4467,10 +4471,6 @@ #define PCI_DID_INTEL_ADL_N_CNVI_WIFI_1 0x54f1 #define PCI_DID_INTEL_ADL_N_CNVI_WIFI_2 0x54f2 #define PCI_DID_INTEL_ADL_N_CNVI_WIFI_3 0x54f3 -#define PCI_DID_INTEL_MTL_CNVI_WIFI_0 0x7e40 -#define PCI_DID_INTEL_MTL_CNVI_WIFI_1 0x7e41 -#define PCI_DID_INTEL_MTL_CNVI_WIFI_2 0x7e42 -#define PCI_DID_INTEL_MTL_CNVI_WIFI_3 0x7e43 /* Intel Crashlog */ #define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d |