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| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2022-03-21 14:06:44 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-23 14:59:12 +0000 |
| commit | 85a09ef99b56ec4e7398efd1d72b388d92435286 (patch) | |
| tree | 676c6cfa6de3b0c826e0a386413aa0fd996af09c /src/include/device/pci_ids.h | |
| parent | a691cbd2eb2a5ed98bf1dadbbe3c09065eb0fe2a (diff) | |
| download | coreboot-85a09ef99b56ec4e7398efd1d72b388d92435286.tar.gz coreboot-85a09ef99b56ec4e7398efd1d72b388d92435286.tar.bz2 coreboot-85a09ef99b56ec4e7398efd1d72b388d92435286.zip | |
soc/intel/adl-n: Add device ID for TCSS XHCI
This patch adds TCSS XHCI device ID for ADL-N CPU which is required
for USB3 port enumeration.
Document Reference: 645548 revision 1.0 (Chapter 2.3)
BUG=None
BRANCH=None
TEST=Check if device is detected correctly and ACPI entries are
generated for device 0d.0
Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/include/device/pci_ids.h')
| -rw-r--r-- | src/include/device/pci_ids.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index d1365f4ac774..ff7d69ad0a5d 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4131,6 +4131,7 @@ #define PCI_DID_INTEL_ADP_P_XHCI 0x51ed #define PCI_DID_INTEL_ADP_S_XHCI 0x7ae0 #define PCI_DID_INTEL_ADP_TCSS_XHCI 0x461e +#define PCI_DID_INTEL_ADP_N_TCSS_XHCI 0x464e #define PCI_DID_INTEL_ADP_M_XHCI 0x54ed #define PCI_DID_INTEL_MTL_XHCI 0x7e7d #define PCI_DID_INTEL_MTL_M_TCSS_XHCI 0x7eb0 |