diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-11-13 15:16:32 -0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-09 22:28:33 +0000 |
| commit | 9f4010753d54447574d7a4e01a11f8b4f810830f (patch) | |
| tree | 24cd4950dbe82f9d2d1dfd543a14b4c63d3802bf /src/include/device/pci_ids.h | |
| parent | 697fa74027402e8eb01c69ee6407599f6cacca75 (diff) | |
| download | coreboot-9f4010753d54447574d7a4e01a11f8b4f810830f.tar.gz coreboot-9f4010753d54447574d7a4e01a11f8b4f810830f.tar.bz2 coreboot-9f4010753d54447574d7a4e01a11f8b4f810830f.zip | |
soc/intel/common: Include Meteor Lake device IDs
Reference: chapter2 in Meteor Lake EDS vol1 (640228)
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62581
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/device/pci_ids.h')
| -rw-r--r-- | src/include/device/pci_ids.h | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 9fa487be2d6d..d1365f4ac774 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2180,6 +2180,7 @@ #define PCI_DID_INTEL_CML_ISHB 0x02fc #define PCI_DID_INTEL_TGL_ISHB 0xa0fc #define PCI_DID_INTEL_TGL_H_ISHB 0x43fc +#define PCI_DID_INTEL_MTL_ISHB 0x7e45 /* Intel 82371FB (PIIX) */ #define PCI_DID_INTEL_82371FB_ISA 0x122e @@ -3074,6 +3075,14 @@ #define PCI_DID_INTEL_ADP_M_N_ESPI_31 0x549f #define PCI_DID_INTEL_ADP_M_ESPI_32 0x5186 #define PCI_DID_INTEL_SPR_ESPI_1 0x1b80 +#define PCI_DID_INTEL_MTL_ESPI_0 0x7e00 +#define PCI_DID_INTEL_MTL_ESPI_1 0x7e01 +#define PCI_DID_INTEL_MTL_ESPI_2 0x7e02 +#define PCI_DID_INTEL_MTL_ESPI_3 0x7e03 +#define PCI_DID_INTEL_MTL_ESPI_4 0x7e04 +#define PCI_DID_INTEL_MTL_ESPI_5 0x7e05 +#define PCI_DID_INTEL_MTL_ESPI_6 0x7e06 +#define PCI_DID_INTEL_MTL_ESPI_7 0x7e07 /* Intel PCIE device ids */ #define PCI_DID_INTEL_LPT_H_PCIE_RP1 0x8c10 @@ -3411,6 +3420,19 @@ #define PCI_DID_INTEL_ADP_N_PCIE_RP11 0x54b2 #define PCI_DID_INTEL_ADP_N_PCIE_RP12 0x54b3 +#define PCI_DID_INTEL_MTL_SOC_PCIE_RP1 0x7e38 +#define PCI_DID_INTEL_MTL_SOC_PCIE_RP2 0x7e39 +#define PCI_DID_INTEL_MTL_SOC_PCIE_RP3 0x7e3a +#define PCI_DID_INTEL_MTL_SOC_PCIE_RP4 0x7e3b +#define PCI_DID_INTEL_MTL_SOC_PCIE_RP5 0x7e3c +#define PCI_DID_INTEL_MTL_SOC_PCIE_RP6 0x7e3d +#define PCI_DID_INTEL_MTL_SOC_PCIE_RP7 0x7e3e +#define PCI_DID_INTEL_MTL_SOC_PCIE_RP8 0x7e3f +#define PCI_DID_INTEL_MTL_SOC_PCIE_RP9 0x7e4d +#define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP10 0x7eca +#define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11 0x7ecb +#define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12 0x7ecc + /* Intel SATA device Ids */ #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE 0x8c00 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI 0x8c02 @@ -3482,6 +3504,7 @@ #define PCI_DID_INTEL_ADP_M_SATA_1 0x54d3 #define PCI_DID_INTEL_ADP_M_SATA_2 0x54d7 #define PCI_DID_INTEL_ADP_M_SATA_3 0x282a +#define PCI_DID_INTEL_MTL_SATA 0x7e63 /* Intel PMC device Ids */ #define PCI_DID_INTEL_SPT_LP_PMC 0x9d21 @@ -3503,6 +3526,9 @@ #define PCI_DID_INTEL_ADP_P_PMC 0x7a21 #define PCI_DID_INTEL_ADP_S_PMC 0x7aa1 #define PCI_DID_INTEL_ADP_M_N_PMC 0x54a1 +#define PCI_DID_INTEL_MTL_SOC_PMC 0x7e21 +#define PCI_DID_INTEL_MTL_IOE_M_PMC 0x7ebe +#define PCI_DID_INTEL_MTL_IOE_P_PMC 0x7ece /* Intel I2C device Ids */ #define PCI_DID_INTEL_LPT_LP_I2C0 0x9c61 @@ -3613,6 +3639,13 @@ #define PCI_DID_INTEL_ADP_M_N_I2C4 0x54c5 #define PCI_DID_INTEL_ADP_M_N_I2C5 0x54c6 +#define PCI_DID_INTEL_MTL_I2C0 0x7e78 +#define PCI_DID_INTEL_MTL_I2C1 0x7e79 +#define PCI_DID_INTEL_MTL_I2C2 0x7e7a +#define PCI_DID_INTEL_MTL_I2C3 0x7e7b +#define PCI_DID_INTEL_MTL_I2C4 0x7e50 +#define PCI_DID_INTEL_MTL_I2C5 0x7e51 + /* Intel UART device Ids */ #define PCI_DID_INTEL_LPT_LP_UART0 0x9c63 #define PCI_DID_INTEL_LPT_LP_UART1 0x9c64 @@ -3683,6 +3716,10 @@ #define PCI_DID_INTEL_ADP_M_N_UART2 0x54c7 #define PCI_DID_INTEL_ADP_M_N_UART3 0x54da +#define PCI_DID_INTEL_MTL_UART0 0x7e25 +#define PCI_DID_INTEL_MTL_UART1 0x7e26 +#define PCI_DID_INTEL_MTL_UART2 0x7e52 + /* Intel SPI device Ids */ #define PCI_DID_INTEL_LPT_LP_GSPI0 0x9c65 #define PCI_DID_INTEL_LPT_LP_GSPI1 0x9c66 @@ -3765,6 +3802,11 @@ #define PCI_DID_INTEL_SPR_HWSEQ_SPI 0x1bca +#define PCI_DID_INTEL_MTL_HWSEQ_SPI 0x7e23 +#define PCI_DID_INTEL_MTL_GSPI0 0x7e27 +#define PCI_DID_INTEL_MTL_GSPI1 0x7e30 +#define PCI_DID_INTEL_MTL_GSPI2 0x7e46 + /* Intel IGD device Ids */ #define PCI_DID_INTEL_SKL_GT1F_DT2 0x1902 #define PCI_DID_INTEL_SKL_GT1_SULTM 0x1906 @@ -3913,6 +3955,9 @@ #define PCI_DID_INTEL_ADL_N_GT1 0x46D0 #define PCI_DID_INTEL_ADL_N_GT2 0x46D1 #define PCI_DID_INTEL_ADL_N_GT3 0x46D2 +#define PCI_DID_INTEL_MTL_M_GT2 0x7d40 +#define PCI_DID_INTEL_MTL_P_GT2_1 0x7d50 +#define PCI_DID_INTEL_MTL_P_GT2_2 0x7d60 /* Intel Northbridge Ids */ @@ -4030,6 +4075,9 @@ #define PCI_DID_INTEL_ADL_N_ID_2 0x461B #define PCI_DID_INTEL_ADL_N_ID_3 0x461c #define PCI_DID_INTEL_ADL_N_ID_4 0x4614 +#define PCI_DID_INTEL_MTL_M_ID 0x7D00 +#define PCI_DID_INTEL_MTL_P_ID_1 0x7D01 +#define PCI_DID_INTEL_MTL_P_ID_2 0x7D02 /* Intel SMBUS device Ids */ #define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22 @@ -4052,6 +4100,7 @@ #define PCI_DID_INTEL_ADP_P_SMBUS 0xa0a3 #define PCI_DID_INTEL_ADP_S_SMBUS 0x7aa3 #define PCI_DID_INTEL_ADP_M_N_SMBUS 0x54a3 +#define PCI_DID_INTEL_MTL_SMBUS 0x7e22 /* Intel EHCI device IDs */ #define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26 @@ -4083,6 +4132,9 @@ #define PCI_DID_INTEL_ADP_S_XHCI 0x7ae0 #define PCI_DID_INTEL_ADP_TCSS_XHCI 0x461e #define PCI_DID_INTEL_ADP_M_XHCI 0x54ed +#define PCI_DID_INTEL_MTL_XHCI 0x7e7d +#define PCI_DID_INTEL_MTL_M_TCSS_XHCI 0x7eb0 +#define PCI_DID_INTEL_MTL_P_TCSS_XHCI 0x7ec0 /* Intel P2SB device Ids */ #define PCI_DID_INTEL_APL_P2SB 0x5a92 @@ -4104,6 +4156,9 @@ #define PCI_DID_INTEL_ADP_P_P2SB 0x7a20 #define PCI_DID_INTEL_ADP_S_P2SB 0x7aa0 #define PCI_DID_INTEL_ADP_M_P2SB 0x54a0 +#define PCI_DID_INTEL_MTL_SOC_P2SB 0x7e20 +#define PCI_DID_INTEL_MTL_IOE_M_P2SB 0x7eb8 +#define PCI_DID_INTEL_MTL_IOE_P_P2SB 0x7ec8 /* Intel SRAM device Ids */ #define PCI_DID_INTEL_APL_SRAM 0x5aec @@ -4116,6 +4171,9 @@ #define PCI_DID_INTEL_TGL_H_SRAM 0x43ef #define PCI_DID_INTEL_MCC_SRAM 0x4b7f #define PCI_DID_INTEL_JSP_SRAM 0x4def +#define PCI_DID_INTEL_MTL_SOC_SRAM 0x7e7f +#define PCI_DID_INTEL_MTL_IOE_M_SRAM 0x7ebf +#define PCI_DID_INTEL_MTL_IOE_P_SRAM 0x7ecf /* Intel AUDIO device Ids */ #define PCI_DID_INTEL_LPT_H_AUDIO 0x8c20 @@ -4155,6 +4213,15 @@ #define PCI_DID_INTEL_ADP_M_N_AUDIO_6 0x54cd #define PCI_DID_INTEL_ADP_M_N_AUDIO_7 0x54ce +#define PCI_DID_INTEL_MTL_AUDIO_1 0x7e28 +#define PCI_DID_INTEL_MTL_AUDIO_2 0x7e29 +#define PCI_DID_INTEL_MTL_AUDIO_3 0x7e2a +#define PCI_DID_INTEL_MTL_AUDIO_4 0x7e2b +#define PCI_DID_INTEL_MTL_AUDIO_5 0x7e2c +#define PCI_DID_INTEL_MTL_AUDIO_6 0x7e2d +#define PCI_DID_INTEL_MTL_AUDIO_7 0x7e2e +#define PCI_DID_INTEL_MTL_AUDIO_8 0x7e2f + /* Intel HECI/ME device Ids */ #define PCI_DID_INTEL_LPT_H_MEI 0x8c3a #define PCI_DID_INTEL_LPT_LP_MEI 0x9c3a @@ -4194,6 +4261,7 @@ #define PCI_DID_INTEL_ADP_M_CSE1 0x54e1 #define PCI_DID_INTEL_ADP_M_CSE2 0x54e4 #define PCI_DID_INTEL_ADP_M_CSE3 0x54e5 +#define PCI_DID_INTEL_MTL_CSE0 0x7e70 /* Intel XDCI device Ids */ #define PCI_DID_INTEL_APL_XDCI 0x5aaa @@ -4213,6 +4281,9 @@ #define PCI_DID_INTEL_ADP_S_XDCI 0x7ae1 #define PCI_DID_INTEL_ADP_TCSS_XDCI 0x460e #define PCI_DID_INTEL_ADP_M_XDCI 0x54ee +#define PCI_DID_INTEL_MTL_XDCI 0x7e7e +#define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1 +#define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1 /* Intel SD device Ids */ #define PCI_DID_INTEL_LPT_LP_SD 0x9c35 @@ -4255,6 +4326,15 @@ #define PCI_DID_INTEL_TGL_H_TBT_DMA1 0x9a21 #define PCI_DID_INTEL_ADL_TBT_DMA0 0x463e #define PCI_DID_INTEL_ADL_TBT_DMA1 0x466d +#define PCI_DID_INTEL_MTL_M_TBT_RP0 0x7eb4 +#define PCI_DID_INTEL_MTL_M_TBT_RP1 0x7eb5 +#define PCI_DID_INTEL_MTL_P_TBT_RP0 0x7ec4 +#define PCI_DID_INTEL_MTL_P_TBT_RP1 0x7ec5 +#define PCI_DID_INTEL_MTL_P_TBT_RP2 0x7ec6 +#define PCI_DID_INTEL_MTL_P_TBT_RP3 0x7ec7 +#define PCI_DID_INTEL_MTL_M_TBT_DMA0 0x7eb2 +#define PCI_DID_INTEL_MTL_P_TBT_DMA0 0x7ec2 +#define PCI_DID_INTEL_MTL_P_TBT_DMA1 0x7ec3 /* Intel WIFI Ids */ #define PCI_DID_1000_SERIES_WIFI 0x0084 @@ -4293,12 +4373,14 @@ #define PCI_DID_INTEL_JSL_IPU 0x4e19 #define PCI_DID_INTEL_ADL_IPU 0x465d #define PCI_DID_INTEL_ADL_N_IPU 0x462e +#define PCI_DID_INTEL_MTL_IPU 0x7d19 /* Intel Dynamic Tuning Technology Device */ #define PCI_DID_INTEL_CML_DTT 0x1903 #define PCI_DID_INTEL_TGL_DTT 0x9A03 #define PCI_DID_INTEL_JSL_DTT 0x4E03 #define PCI_DID_INTEL_ADL_DTT 0x461d +#define PCI_DID_INTEL_MTL_DTT 0x7d03 /* Intel CNVi WiFi/BT device IDs */ #define PCI_DID_INTEL_CML_LP_CNVI_WIFI 0x02f0 @@ -4330,6 +4412,10 @@ #define PCI_DID_INTEL_ADL_N_CNVI_WIFI_1 0x54f1 #define PCI_DID_INTEL_ADL_N_CNVI_WIFI_2 0x54f2 #define PCI_DID_INTEL_ADL_N_CNVI_WIFI_3 0x54f3 +#define PCI_DID_INTEL_MTL_CNVI_WIFI_0 0x7e40 +#define PCI_DID_INTEL_MTL_CNVI_WIFI_1 0x7e41 +#define PCI_DID_INTEL_MTL_CNVI_WIFI_2 0x7e42 +#define PCI_DID_INTEL_MTL_CNVI_WIFI_3 0x7e43 /* Intel Crashlog */ #define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d @@ -4338,6 +4424,7 @@ #define PCI_DID_INTEL_ADP_P_PMC_CRASHLOG_SRAM 0x51ef #define PCI_DID_INTEL_ADP_N_PMC_CRASHLOG_SRAM 0x54ef #define PCI_DID_INTEL_TGP_PMC_CRASHLOG_SRAM 0xa0ef +#define PCI_DID_INTEL_MTL_CRASHLOG_SRAM 0x7d0d #define PCI_VID_COMPUTONE 0x8e0e #define PCI_DID_COMPUTONE_IP2EX 0x0291 |