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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-11-15 22:47:33 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-20 13:34:45 +0000 |
| commit | efe3cfb476b39da5ece2583000e0f24b5daf560b (patch) | |
| tree | d1ba7be71d4c58a2b087cedb996dd1d08b01a52f /src/include/device/pci_mmio_cfg.h | |
| parent | 12487319913e8b8c9ea4acc946e37ccbcd6e3909 (diff) | |
| download | coreboot-efe3cfb476b39da5ece2583000e0f24b5daf560b.tar.gz coreboot-efe3cfb476b39da5ece2583000e0f24b5daf560b.tar.bz2 coreboot-efe3cfb476b39da5ece2583000e0f24b5daf560b.zip | |
include/device: add a comment to pci mmio cfg addr helpers and caching
Add a comment to the newly introduced MMIO address helpers for PCI
config registers, that the pointer returned may change during the boot
processs and, thus, must not be cached.
Change-Id: Ieb90ae9d67a3b944d35587dec54756a17c27c86f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include/device/pci_mmio_cfg.h')
| -rw-r--r-- | src/include/device/pci_mmio_cfg.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index 8f26ff29b0d2..30945f4c2785 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -86,6 +86,12 @@ void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) pcicfg(dev)->reg32[reg / sizeof(uint32_t)] = value; } +/* + * The functions pci_mmio_config*_addr provide a way to determine the MMIO address of a PCI + * config register. The address returned is dependent of both the MMCONF base address and the + * assigned PCI bus number of the requested device, which both can change during the boot + * process. Thus, the pointer returned here must not be cached! + */ static __always_inline uint8_t *pci_mmio_config8_addr(pci_devfn_t dev, uint16_t reg) { |